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altera-fpga2sdram-bridge.txt
(353 B)
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altera-freeze-bridge.txt
(697 B)
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altera-hps2fpga-bridge.txt
(1.02 KB)
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altera-passive-serial.txt
(988 B)
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altera-pr-ip.txt
(276 B)
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altera-socfpga-a10-fpga-mgr.txt
(629 B)
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altera-socfpga-fpga-mgr.txt
(533 B)
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fpga-bridge.txt
(367 B)
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fpga-region.txt
(17.25 KB)
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intel-stratix10-soc-fpga-mgr.txt
(372 B)
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lattice-ice40-fpga-mgr.txt
(729 B)
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lattice-machxo2-spi.txt
(656 B)
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xilinx-pr-decoupler.txt
(1.12 KB)
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xilinx-slave-serial.txt
(1.62 KB)
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xilinx-zynq-fpga-mgr.txt
(560 B)
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xlnx,zynqmp-pcap-fpga.txt
(641 B)
Editing: altera-socfpga-a10-fpga-mgr.txt
Altera SOCFPGA Arria10 FPGA Manager Required properties: - compatible : should contain "altr,socfpga-a10-fpga-mgr" - reg : base address and size for memory mapped io. - The first index is for FPGA manager register access. - The second index is for writing FPGA configuration data. - resets : Phandle and reset specifier for the device's reset. - clocks : Clocks used by the device. Example: fpga_mgr: fpga-mgr@ffd03000 { compatible = "altr,socfpga-a10-fpga-mgr"; reg = <0xffd03000 0x100 0xffcfe400 0x20>; clocks = <&l4_mp_clk>; resets = <&rst FPGAMGR_RESET>; };
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