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adpll.txt
(1.4 KB)
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apll.txt
(1.78 KB)
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autoidle.txt
(1.2 KB)
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clockdomain.txt
(880 B)
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composite.txt
(1.59 KB)
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davinci
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divider.txt
(3.68 KB)
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dpll.txt
(2.86 KB)
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dra7-atl.txt
(2.81 KB)
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fapll.txt
(1.04 KB)
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fixed-factor-clock.txt
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gate.txt
(3.26 KB)
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interface.txt
(1.96 KB)
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mux.txt
(2.58 KB)
Editing: apll.txt
Binding for Texas Instruments APLL clock. Binding status: Unstable - ABI compatibility may be broken in the future This binding uses the common clock binding[1]. It assumes a register-mapped APLL with usually two selectable input clocks (reference clock and bypass clock), with analog phase locked loop logic for multiplying the input clock to a desired output clock. This clock also typically supports different operation modes (locked, low power stop etc.) APLL mostly behaves like a subtype of a DPLL [2], although a simplified one at that. [1] Documentation/devicetree/bindings/clock/clock-bindings.txt [2] Documentation/devicetree/bindings/clock/ti/dpll.txt Required properties: - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock" - #clock-cells : from common clock binding; shall be set to 0. - clocks : link phandles of parent clocks (clk-ref and clk-bypass) - reg : address and length of the register set for controlling the APLL. It contains the information of registers in the following order: "control" - contains the control register offset "idlest" - contains the idlest register offset "autoidle" - contains the autoidle register offset (OMAP2 only) - ti,clock-frequency : static clock frequency for the clock (OMAP2 only) - ti,idlest-shift : bit-shift for the idlest field (OMAP2 only) - ti,bit-shift : bit-shift for enable and autoidle fields (OMAP2 only) Examples: apll_pcie_ck: apll_pcie_ck { #clock-cells = <0>; clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; reg = <0x021c>, <0x0220>; compatible = "ti,dra7-apll-clock"; }; apll96_ck: apll96_ck { #clock-cells = <0>; compatible = "ti,omap2-apll-clock"; clocks = <&sys_ck>; ti,bit-shift = <2>; ti,idlest-shift = <8>; ti,clock-frequency = <96000000>; reg = <0x0500>, <0x0530>, <0x0520>; };
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