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cache_sram.txt
(559 B)
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ccf.txt
(1.37 KB)
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cpus.txt
(1.43 KB)
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dcsr.txt
(10.72 KB)
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diu.txt
(847 B)
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dma.txt
(6.56 KB)
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ecm.txt
(1.81 KB)
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interlaken-lac.txt
(8.59 KB)
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l2cache.txt
(2.03 KB)
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lbc.txt
(1.11 KB)
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mcm.txt
(1.81 KB)
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mcu-mpc8349emitx.txt
(428 B)
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mpc5121-psc.txt
(2.4 KB)
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mpc512x_lpbfifo.txt
(669 B)
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mpc5200.txt
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mpic-msgr.txt
(2.35 KB)
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mpic-timer.txt
(1.14 KB)
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mpic.txt
(7.33 KB)
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msi-pic.txt
(4.38 KB)
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pamu.txt
(4.78 KB)
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pmc.txt
(2.48 KB)
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raideng.txt
(2.47 KB)
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scfg.txt
(451 B)
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srio-rmu.txt
(5.12 KB)
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srio.txt
(3.34 KB)
Editing: ccf.txt
Freescale CoreNet Coherency Fabric(CCF) Device Tree Binding DESCRIPTION The CoreNet coherency fabric is a fabric-oriented, connectivity infrastructure that enables the implementation of coherent, multicore systems. Required properties: - compatible: <string list> fsl,corenet1-cf - CoreNet coherency fabric version 1. Example chips: T4240, B4860 fsl,corenet2-cf - CoreNet coherency fabric version 2. Example chips: P5040, P5020, P4080, P3041, P2041 fsl,corenet-cf - Used to represent the common registers between CCF version 1 and CCF version 2. This compatible is retained for compatibility reasons, as it was already used for both CCF version 1 chips and CCF version 2 chips. It should be specified after either "fsl,corenet1-cf" or "fsl,corenet2-cf". - reg: <prop-encoded-array> A standard property. Represents the CCF registers. - interrupts: <prop-encoded-array> Interrupt mapping for CCF error interrupt. - fsl,ccf-num-csdids: <u32> Specifies the number of Coherency Subdomain ID Port Mapping Registers that are supported by the CCF. - fsl,ccf-num-snoopids: <u32> Specifies the number of Snoop ID Port Mapping Registers that are supported by CCF. Example: corenet-cf@18000 { compatible = "fsl,corenet2-cf", "fsl,corenet-cf"; reg = <0x18000 0x1000>; interrupts = <16 2 1 31>; fsl,ccf-num-csdids = <32>; fsl,ccf-num-snoopids = <32>; };
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