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_align.h
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_bus.h
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_inttypes.h
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_limits.h
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_stdint.h
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_types.h
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abi.h
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asm.h
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atomic.h
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bootinfo.h
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bus.h
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bus_dma.h
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cache.h
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cache_mipsNN.h
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cache_r4k.h
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cca.h
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cdefs.h
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clock.h
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counter.h
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cpu.h
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cpufunc.h
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cpuinfo.h
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cpuregs.h
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db_machdep.h
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dump.h
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efi.h
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elf.h
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endian.h
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exec.h
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fdt.h
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float.h
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floatingpoint.h
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fls64.h
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fpu.h
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frame.h
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gdb_machdep.h
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hwfunc.h
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ieee.h
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ieeefp.h
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in_cksum.h
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intr.h
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intr_machdep.h
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kdb.h
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limits.h
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locore.h
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md_var.h
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memdev.h
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metadata.h
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minidump.h
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mips_opcode.h
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octeon_cop2.h
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ofw_machdep.h
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param.h
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pcb.h
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pcpu.h
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pcpu_aux.h
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pmap.h
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pmc_mdep.h
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proc.h
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procctl.h
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profile.h
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pte.h
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ptrace.h
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reg.h
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regdef.h
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regnum.h
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reloc.h
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resource.h
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runq.h
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sc_machdep.h
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setjmp.h
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sf_buf.h
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sigframe.h
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signal.h
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smp.h
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stdarg.h
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sysarch.h
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tlb.h
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tls.h
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trap.h
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ucontext.h
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vdso.h
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vm.h
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vmparam.h
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Editing: cdefs.h
/* $NetBSD: cdefs.h,v 1.12 2006/08/27 19:04:30 matt Exp $ */ /*- * SPDX-License-Identifier: MIT-CMU * * Copyright (c) 1995 Carnegie-Mellon University. * All rights reserved. * * Author: Chris G. Demetriou * * Permission to use, copy, modify and distribute this software and * its documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. * * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. * * Carnegie Mellon requests users of this software to return to * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU * School of Computer Science * Carnegie Mellon University * Pittsburgh PA 15213-3890 * * any improvements or extensions that they make and grant Carnegie the * rights to redistribute these changes. * * $FreeBSD$ */ #ifndef _MIPS_CDEFS_H_ #define _MIPS_CDEFS_H_ /* * These are depreciated. Use __mips_{o32,o64,n32,n64} instead. */ /* MIPS Subprogram Interface Model */ #define _MIPS_SIM_ABIX32 4 /* 64 bit safe, ILP32 o32 model */ #define _MIPS_SIM_ABI64 3 #define _MIPS_SIM_NABI32 2 /* 64bit safe, ILP32 n32 model */ #define _MIPS_SIM_ABI32 1 #define _MIPS_BSD_API_LP32 _MIPS_SIM_ABI32 #define _MIPS_BSD_API_LP32_64CLEAN _MIPS_SIM_ABIX32 #define _MIPS_BSD_API_LP64 _MIPS_SIM_ABI64 #define _MIPS_BSD_API_O32 _MIPS_SIM_ABI32 #define _MIPS_BSD_API_O64 _MIPS_SIM_ABIX32 #define _MIPS_BSD_API_N32 _MIPS_SIM_NABI32 #define _MIPS_BSD_API_N64 _MIPS_SIM_ABI64 #define _MIPS_SIM_NEWABI_P(abi) ((abi) == _MIPS_SIM_NABI32 || \ (abi) == _MIPS_SIM_ABI64) #define _MIPS_SIM_LP64_P(abi) ((abi) == _MIPS_SIM_ABIX32 || \ (abi) == _MIPS_SIM_ABI64) #if defined(__mips_n64) #define _MIPS_BSD_API _MIPS_BSD_API_N64 #elif defined(__mips_n32) #define _MIPS_BSD_API _MIPS_BSD_API_N32 #elif defined(__mips_o64) #define _MIPS_BSD_API _MIPS_BSD_API_O64 #else #define _MIPS_BSD_API _MIPS_BSD_API_O32 #endif #define _MIPS_ISA_MIPS1 1 #define _MIPS_ISA_MIPS2 2 #define _MIPS_ISA_MIPS3 3 #define _MIPS_ISA_MIPS4 4 #define _MIPS_ISA_MIPS32 5 #define _MIPS_ISA_MIPS64 6 #endif /* !_MIPS_CDEFS_H_ */
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