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📄 README.txt(14.85 KB)
📁 aarch64
📄 absvdi2.c(815 B)
📄 absvsi2.c(815 B)
📄 absvti2.c(864 B)
📄 adddf3.c(859 B)
📄 addsf3.c(853 B)
📄 addtf3.c(730 B)
📄 addvdi3.c(819 B)
📄 addvsi3.c(819 B)
📄 addvti3.c(868 B)
📄 apple_versioning.c(13.1 KB)
📁 arm
📄 ashldi3.c(1.17 KB)
📄 ashlti3.c(1.15 KB)
📄 ashrdi3.c(1.27 KB)
📄 ashrti3.c(1.25 KB)
📄 assembly.h(7.11 KB)
📄 atomic.c(16.86 KB)
📄 atomic_flag_clear.c(791 B)
📄 atomic_flag_clear_explicit.c(859 B)
📄 atomic_flag_test_and_set.c(823 B)
📄 atomic_flag_test_and_set_explicit.c(898 B)
📄 atomic_signal_fence.c(761 B)
📄 atomic_thread_fence.c(761 B)
📄 bswapdi2.c(958 B)
📄 bswapsi2.c(743 B)
📄 clear_cache.c(6.13 KB)
📄 clzdi2.c(1.27 KB)
📄 clzsi2.c(1.48 KB)
📄 clzti2.c(884 B)
📄 cmpdi2.c(1.12 KB)
📄 cmpti2.c(974 B)
📄 comparedf2.c(4.29 KB)
📄 comparesf2.c(4.28 KB)
📄 comparetf2.c(3.79 KB)
📄 cpu_model.c(21.28 KB)
📄 ctzdi2.c(1.27 KB)
📄 ctzsi2.c(1.61 KB)
📄 ctzti2.c(884 B)
📄 divdc3.c(2.18 KB)
📄 divdf3.c(7.55 KB)
📄 divdi3.c(1.13 KB)
📄 divmoddi4.c(712 B)
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📄 divsc3.c(2.14 KB)
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📄 divsi3.c(1.32 KB)
📄 divtc3.c(2.23 KB)
📄 divtf3.c(8.01 KB)
📄 divti3.c(1.18 KB)
📄 divxc3.c(2.17 KB)
📄 emutls.c(12.39 KB)
📄 enable_execute_stack.c(2.08 KB)
📄 eprintf.c(953 B)
📄 extenddftf2.c(623 B)
📄 extendhfsf2.c(946 B)
📄 extendsfdf2.c(716 B)
📄 extendsftf2.c(622 B)
📄 ffsdi2.c(900 B)
📄 ffssi2.c(776 B)
📄 ffsti2.c(969 B)
📄 fixdfdi.c(1.22 KB)
📄 fixdfsi.c(755 B)
📄 fixdfti.c(633 B)
📄 fixsfdi.c(1.22 KB)
📄 fixsfsi.c(755 B)
📄 fixsfti.c(633 B)
📄 fixtfdi.c(624 B)
📄 fixtfsi.c(624 B)
📄 fixtfti.c(624 B)
📄 fixunsdfdi.c(1.29 KB)
📄 fixunsdfsi.c(743 B)
📄 fixunsdfti.c(611 B)
📄 fixunssfdi.c(1.3 KB)
📄 fixunssfsi.c(896 B)
📄 fixunssfti.c(731 B)
📄 fixunstfdi.c(604 B)
📄 fixunstfsi.c(604 B)
📄 fixunstfti.c(604 B)
📄 fixunsxfdi.c(1.65 KB)
📄 fixunsxfsi.c(1.62 KB)
📄 fixunsxfti.c(1.41 KB)
📄 fixxfdi.c(1.75 KB)
📄 fixxfti.c(1.48 KB)
📄 floatdidf.c(3.37 KB)
📄 floatdisf.c(2.49 KB)
📄 floatditf.c(1.5 KB)
📄 floatdixf.c(1.37 KB)
📄 floatsidf.c(1.7 KB)
📄 floatsisf.c(1.89 KB)
📄 floatsitf.c(1.5 KB)
📄 floattidf.c(2.49 KB)
📄 floattisf.c(2.33 KB)
📄 floattitf.c(2.72 KB)
📄 floattixf.c(2.53 KB)
📄 floatundidf.c(3.43 KB)
📄 floatundisf.c(2.4 KB)
📄 floatunditf.c(1.27 KB)
📄 floatundixf.c(1.24 KB)
📄 floatunsidf.c(1.43 KB)
📄 floatunsisf.c(1.75 KB)
📄 floatunsitf.c(1.29 KB)
📄 floatuntidf.c(2.38 KB)
📄 floatuntisf.c(2.24 KB)
📄 floatuntitf.c(2.6 KB)
📄 floatuntixf.c(2.39 KB)
📄 fp_add_impl.inc(5.4 KB)
📄 fp_extend.h(2.36 KB)
📄 fp_extend_impl.inc(4.53 KB)
📄 fp_fixint_impl.inc(1.52 KB)
📄 fp_fixuint_impl.inc(1.42 KB)
📄 fp_lib.h(10.12 KB)
📄 fp_mode.c(812 B)
📄 fp_mode.h(824 B)
📄 fp_mul_impl.inc(4.37 KB)
📄 fp_trunc.h(2.01 KB)
📄 fp_trunc_impl.inc(5.57 KB)
📄 gcc_personality_v0.c(8.3 KB)
📁 hexagon
📁 i386
📄 int_div_impl.inc(2.19 KB)
📄 int_endianness.h(2.75 KB)
📄 int_lib.h(4.57 KB)
📄 int_math.h(3.6 KB)
📄 int_types.h(4.16 KB)
📄 int_util.c(1.95 KB)
📄 int_util.h(1.32 KB)
📄 lshrdi3.c(1.18 KB)
📄 lshrti3.c(1.17 KB)
📄 mingw_fixfloat.c(1.29 KB)
📄 moddi3.c(1004 B)
📄 modsi3.c(649 B)
📄 modti3.c(1.03 KB)
📄 muldc3.c(2.14 KB)
📄 muldf3.c(918 B)
📄 muldi3.c(1.55 KB)
📄 mulodi4.c(1.31 KB)
📄 mulosi4.c(1.31 KB)
📄 muloti4.c(1.36 KB)
📄 mulsc3.c(2.11 KB)
📄 mulsf3.c(918 B)
📄 multc3.c(2.02 KB)
📄 multf3.c(799 B)
📄 multi3.c(1.53 KB)
📄 mulvdi3.c(1.26 KB)
📄 mulvsi3.c(1.26 KB)
📄 mulvti3.c(1.31 KB)
📄 mulxc3.c(2.22 KB)
📄 negdf2.c(832 B)
📄 negdi2.c(719 B)
📄 negsf2.c(832 B)
📄 negti2.c(768 B)
📄 negvdi2.c(768 B)
📄 negvsi2.c(768 B)
📄 negvti2.c(817 B)
📄 os_version_check.c(8.07 KB)
📄 paritydi2.c(712 B)
📄 paritysi2.c(751 B)
📄 parityti2.c(761 B)
📄 popcountdi2.c(1.33 KB)
📄 popcountsi2.c(1.13 KB)
📄 popcountti2.c(1.69 KB)
📄 powidf2.c(786 B)
📄 powisf2.c(783 B)
📄 powitf2.c(888 B)
📄 powixf2.c(825 B)
📁 ppc
📁 riscv
📁 sparc64
📄 subdf3.c(917 B)
📄 subsf3.c(917 B)
📄 subtf3.c(825 B)
📄 subvdi3.c(819 B)
📄 subvsi3.c(819 B)
📄 subvti3.c(868 B)
📄 trampoline_setup.c(1.75 KB)
📄 truncdfhf2.c(715 B)
📄 truncdfsf2.c(711 B)
📄 truncsfhf2.c(940 B)
📄 trunctfdf2.c(625 B)
📄 trunctfsf2.c(624 B)
📄 ucmpdi2.c(1.13 KB)
📄 ucmpti2.c(978 B)
📄 udivdi3.c(724 B)
📄 udivmoddi4.c(5.4 KB)
📄 udivmodsi4.c(715 B)
📄 udivmodti4.c(4.87 KB)
📄 udivsi3.c(802 B)
📄 udivti3.c(699 B)
📄 umoddi3.c(724 B)
📄 umodsi3.c(724 B)
📄 umodti3.c(717 B)
📄 unwind-ehabi-helpers.h(1.86 KB)
📁 ve
📁 x86_64

Editing: clear_cache.c

//===-- clear_cache.c - Implement __clear_cache ---------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

#include "int_lib.h"
#include <assert.h>
#include <stddef.h>

#if __APPLE__
#include <libkern/OSCacheControl.h>
#endif

#if defined(_WIN32)
// Forward declare Win32 APIs since the GCC mode driver does not handle the
// newer SDKs as well as needed.
uint32_t FlushInstructionCache(uintptr_t hProcess, void *lpBaseAddress,
                               uintptr_t dwSize);
uintptr_t GetCurrentProcess(void);
#endif

#if defined(__FreeBSD__) && defined(__arm__)
// clang-format off
#include <sys/types.h>
#include <machine/sysarch.h>
// clang-format on
#endif

#if defined(__NetBSD__) && defined(__arm__)
#include <machine/sysarch.h>
#endif

#if defined(__OpenBSD__) && (defined(__arm__) || defined(__mips__))
// clang-format off
#include <sys/types.h>
#include <machine/sysarch.h>
// clang-format on
#endif

#if defined(__linux__) && defined(__mips__)
#include <sys/cachectl.h>
#include <sys/syscall.h>
#include <unistd.h>
#endif

// The compiler generates calls to __clear_cache() when creating
// trampoline functions on the stack for use with nested functions.
// It is expected to invalidate the instruction cache for the
// specified range.

void __clear_cache(void *start, void *end) {
#if __i386__ || __x86_64__ || defined(_M_IX86) || defined(_M_X64)
// Intel processors have a unified instruction and data cache
// so there is nothing to do
#elif defined(_WIN32) && (defined(__arm__) || defined(__aarch64__))
  FlushInstructionCache(GetCurrentProcess(), start, end - start);
#elif defined(__arm__) && !defined(__APPLE__)
#if defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__)
  struct arm_sync_icache_args arg;

arg.addr = (uintptr_t)start;
  arg.len = (uintptr_t)end - (uintptr_t)start;

sysarch(ARM_SYNC_ICACHE, &arg);
#elif defined(__linux__)
// We used to include asm/unistd.h for the __ARM_NR_cacheflush define, but
// it also brought many other unused defines, as well as a dependency on
// kernel headers to be installed.
//
// This value is stable at least since Linux 3.13 and should remain so for
// compatibility reasons, warranting it's re-definition here.
#define __ARM_NR_cacheflush 0x0f0002
  register int start_reg __asm("r0") = (int)(intptr_t)start;
  const register int end_reg __asm("r1") = (int)(intptr_t)end;
  const register int flags __asm("r2") = 0;
  const register int syscall_nr __asm("r7") = __ARM_NR_cacheflush;
  __asm __volatile("svc 0x0"
                   : "=r"(start_reg)
                   : "r"(syscall_nr), "r"(start_reg), "r"(end_reg), "r"(flags));
  assert(start_reg == 0 && "Cache flush syscall failed.");
#else
  compilerrt_abort();
#endif
#elif defined(__linux__) && defined(__mips__)
  const uintptr_t start_int = (uintptr_t)start;
  const uintptr_t end_int = (uintptr_t)end;
  syscall(__NR_cacheflush, start, (end_int - start_int), BCACHE);
#elif defined(__mips__) && defined(__OpenBSD__)
  cacheflush(start, (uintptr_t)end - (uintptr_t)start, BCACHE);
#elif defined(__aarch64__) && !defined(__APPLE__)
  uint64_t xstart = (uint64_t)(uintptr_t)start;
  uint64_t xend = (uint64_t)(uintptr_t)end;

// Get Cache Type Info.
  static uint64_t ctr_el0 = 0;
  if (ctr_el0 == 0)
    __asm __volatile("mrs %0, ctr_el0" : "=r"(ctr_el0));

// The DC and IC instructions must use 64-bit registers so we don't use
  // uintptr_t in case this runs in an IPL32 environment.
  uint64_t addr;

// If CTR_EL0.IDC is set, data cache cleaning to the point of unification
  // is not required for instruction to data coherence.
  if (((ctr_el0 >> 28) & 0x1) == 0x0) {
    const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15);
    for (addr = xstart & ~(dcache_line_size - 1); addr < xend;
         addr += dcache_line_size)
      __asm __volatile("dc cvau, %0" ::"r"(addr));
  }
  __asm __volatile("dsb ish");

// If CTR_EL0.DIC is set, instruction cache invalidation to the point of
  // unification is not required for instruction to data coherence.
  if (((ctr_el0 >> 29) & 0x1) == 0x0) {
    const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15);
    for (addr = xstart & ~(icache_line_size - 1); addr < xend;
         addr += icache_line_size)
      __asm __volatile("ic ivau, %0" ::"r"(addr));
  }
  __asm __volatile("isb sy");
#elif defined(__powerpc64__)
  const size_t line_size = 32;
  const size_t len = (uintptr_t)end - (uintptr_t)start;

const uintptr_t mask = ~(line_size - 1);
  const uintptr_t start_line = ((uintptr_t)start) & mask;
  const uintptr_t end_line = ((uintptr_t)start + len + line_size - 1) & mask;

for (uintptr_t line = start_line; line < end_line; line += line_size)
    __asm__ volatile("dcbf 0, %0" : : "r"(line));
  __asm__ volatile("sync");

for (uintptr_t line = start_line; line < end_line; line += line_size)
    __asm__ volatile("icbi 0, %0" : : "r"(line));
  __asm__ volatile("isync");
#elif defined(__sparc__)
  const size_t dword_size = 8;
  const size_t len = (uintptr_t)end - (uintptr_t)start;

const uintptr_t mask = ~(dword_size - 1);
  const uintptr_t start_dword = ((uintptr_t)start) & mask;
  const uintptr_t end_dword = ((uintptr_t)start + len + dword_size - 1) & mask;

for (uintptr_t dword = start_dword; dword < end_dword; dword += dword_size)
    __asm__ volatile("flush %0" : : "r"(dword));
#elif defined(__riscv) && defined(__linux__)
#define __NR_riscv_flush_icache (244 + 15)
  register void *start_reg __asm("a0") = start;
  const register void *end_reg __asm("a1") = end;
  const register long flags __asm("a2") = 0;
  const register long syscall_nr __asm("a7") = __NR_riscv_flush_icache;
  __asm __volatile("ecall"
                   : "=r"(start_reg)
                   : "r"(start_reg), "r"(end_reg), "r"(flags), "r"(syscall_nr));
  assert(start_reg == 0 && "Cache flush syscall failed.");
#else
#if __APPLE__
  // On Darwin, sys_icache_invalidate() provides this functionality
  sys_icache_invalidate(start, end - start);
#else
  compilerrt_abort();
#endif
#endif
}

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Editing: clear_cache.c

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