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📄 _inttypes.h(7.91 KB)
📄 _limits.h(3.63 KB)
📄 _stdint.h(4.82 KB)
📄 _types.h(3.66 KB)
📄 acpica_machdep.h(2.27 KB)
📄 armreg.h(47.3 KB)
📄 asm.h(3.52 KB)
📄 atomic.h(17.74 KB)
📄 bus.h(19.24 KB)
📄 bus_dma.h(3.83 KB)
📄 bus_dma_impl.h(4.09 KB)
📄 clock.h(16 B)
📄 counter.h(2.45 KB)
📄 cpu.h(6.81 KB)
📄 cpufunc.h(4.97 KB)
📄 csan.h(2.73 KB)
📄 db_machdep.h(5.3 KB)
📄 debug_monitor.h(2.36 KB)
📄 disassem.h(1.67 KB)
📄 dump.h(2.26 KB)
📄 efi.h(2.02 KB)
📄 elf.h(4.66 KB)
📄 endian.h(3.57 KB)
📄 exec.h(16 B)
📄 float.h(3.56 KB)
📄 floatingpoint.h(45 B)
📄 fpu.h(87 B)
📄 frame.h(2.38 KB)
📄 gdb_machdep.h(2.4 KB)
📄 hypervisor.h(7.23 KB)
📄 ieeefp.h(1.23 KB)
📄 ifunc.h(2.28 KB)
📄 in_cksum.h(2.18 KB)
📄 intr.h(1.81 KB)
📄 iodev.h(2.23 KB)
📄 iommu.h(180 B)
📄 kdb.h(1.89 KB)
📄 machdep.h(2.15 KB)
📄 md_var.h(2.5 KB)
📄 memdev.h(1.55 KB)
📄 metadata.h(1.87 KB)
📄 minidump.h(1.75 KB)
📄 ofw_machdep.h(1.65 KB)
📄 param.h(3.77 KB)
📄 pcb.h(2.61 KB)
📄 pci_cfgreg.h(1.57 KB)
📄 pcpu.h(2.61 KB)
📄 pcpu_aux.h(1.94 KB)
📄 pmap.h(6.57 KB)
📄 pmc_mdep.h(2.21 KB)
📄 proc.h(2.37 KB)
📄 procctl.h(62 B)
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📄 pte.h(5.21 KB)
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📄 reg.h(2.94 KB)
📄 reloc.h(16 B)
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📄 setjmp.h(2.69 KB)
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📄 stdarg.h(1.58 KB)
📄 sysarch.h(1.86 KB)
📄 trap.h(16 B)
📄 ucontext.h(2.65 KB)
📄 undefined.h(2.27 KB)
📄 vdso.h(1.57 KB)
📄 vfp.h(3.65 KB)
📄 vm.h(1.8 KB)
📄 vmparam.h(7.44 KB)

Editing: cpufunc.h

/*-
 * Copyright (c) 2014 Andrew Turner
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * $FreeBSD$
 */

#ifndef _MACHINE_CPUFUNC_H_
#define	_MACHINE_CPUFUNC_H_

static __inline void
breakpoint(void)
{

__asm("brk #0");
}

#ifdef _KERNEL

#define	HAVE_INLINE_FFS

static __inline __pure2 int
ffs(int mask)
{

return (__builtin_ffs(mask));
}

#define	HAVE_INLINE_FFSL

static __inline __pure2 int
ffsl(long mask)
{

return (__builtin_ffsl(mask));
}

#define	HAVE_INLINE_FFSLL

static __inline __pure2 int
ffsll(long long mask)
{

return (__builtin_ffsll(mask));
}

#define	HAVE_INLINE_FLS

static __inline __pure2 int
fls(int mask)
{

return (mask == 0 ? 0 :
	    8 * sizeof(mask) - __builtin_clz((u_int)mask));
}

#define	HAVE_INLINE_FLSL

static __inline __pure2 int
flsl(long mask)
{

return (mask == 0 ? 0 :
	    8 * sizeof(mask) - __builtin_clzl((u_long)mask));
}

#define	HAVE_INLINE_FLSLL

static __inline __pure2 int
flsll(long long mask)
{

return (mask == 0 ? 0 :
	    8 * sizeof(mask) - __builtin_clzll((unsigned long long)mask));
}

#include <machine/armreg.h>

void pan_enable(void);

static __inline register_t
dbg_disable(void)
{
	uint32_t ret;

__asm __volatile(
	    "mrs %x0, daif   \n"
	    "msr daifset, #8 \n"
	    : "=&r" (ret));

return (ret);
}

static __inline void
dbg_enable(void)
{

__asm __volatile("msr daifclr, #8");
}

static __inline register_t
intr_disable(void)
{
	/* DAIF is a 32-bit register */
	uint32_t ret;

__asm __volatile(
	    "mrs %x0, daif   \n"
	    "msr daifset, #2 \n"
	    : "=&r" (ret));

return (ret);
}

static __inline void
intr_restore(register_t s)
{

WRITE_SPECIALREG(daif, s);
}

static __inline void
intr_enable(void)
{

__asm __volatile("msr daifclr, #2");
}

static __inline register_t
get_midr(void)
{
	uint64_t midr;

midr = READ_SPECIALREG(midr_el1);

return (midr);
}

static __inline register_t
get_mpidr(void)
{
	uint64_t mpidr;

mpidr = READ_SPECIALREG(mpidr_el1);

return (mpidr);
}

static __inline void
clrex(void)
{

/*
	 * Ensure compiler barrier, otherwise the monitor clear might
	 * occur too late for us ?
	 */
	__asm __volatile("clrex" : : : "memory");
}

static __inline void
set_ttbr0(uint64_t ttbr0)
{

__asm __volatile(
	    "msr ttbr0_el1, %0 \n"
	    "isb               \n"
	    :
	    : "r" (ttbr0));
}

static __inline void
invalidate_icache(void)
{

__asm __volatile(
	    "ic ialluis        \n"
	    "dsb ish           \n"
	    "isb               \n");
}

static __inline void
invalidate_local_icache(void)
{

__asm __volatile(
	    "ic iallu          \n"
	    "dsb nsh           \n"
	    "isb               \n");
}

extern bool icache_aliasing;
extern bool icache_vmid;

extern int64_t dcache_line_size;
extern int64_t icache_line_size;
extern int64_t idcache_line_size;
extern int64_t dczva_line_size;

#define	cpu_nullop()			arm64_nullop()
#define	cpufunc_nullop()		arm64_nullop()

#define	cpu_tlb_flushID()		arm64_tlb_flushID()

#define	cpu_dcache_wbinv_range(a, s)	arm64_dcache_wbinv_range((a), (s))
#define	cpu_dcache_inv_range(a, s)	arm64_dcache_inv_range((a), (s))
#define	cpu_dcache_wb_range(a, s)	arm64_dcache_wb_range((a), (s))

extern void (*arm64_icache_sync_range)(vm_offset_t, vm_size_t);

#define	cpu_icache_sync_range(a, s)	arm64_icache_sync_range((a), (s))
#define cpu_icache_sync_range_checked(a, s) arm64_icache_sync_range_checked((a), (s))

void arm64_nullop(void);
void arm64_tlb_flushID(void);
void arm64_dic_idc_icache_sync_range(vm_offset_t, vm_size_t);
void arm64_aliasing_icache_sync_range(vm_offset_t, vm_size_t);
int arm64_icache_sync_range_checked(vm_offset_t, vm_size_t);
void arm64_dcache_wbinv_range(vm_offset_t, vm_size_t);
void arm64_dcache_inv_range(vm_offset_t, vm_size_t);
void arm64_dcache_wb_range(vm_offset_t, vm_size_t);

#endif	/* _KERNEL */
#endif	/* _MACHINE_CPUFUNC_H_ */

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Editing: cpufunc.h

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