003 File Manager
Current Path:
/usr/src/sys/arm64/arm64
usr
/
src
/
sys
/
arm64
/
arm64
/
📁
..
📄
autoconf.c
(2.78 KB)
📄
bus_machdep.c
(8.05 KB)
📄
bus_space_asm.S
(8.08 KB)
📄
busdma_bounce.c
(40.82 KB)
📄
busdma_machdep.c
(7.46 KB)
📄
bzero.S
(5.33 KB)
📄
clock.c
(1.47 KB)
📄
copyinout.S
(5.31 KB)
📄
cpu_errata.c
(5.14 KB)
📄
cpufunc_asm.S
(4.71 KB)
📄
db_disasm.c
(2.26 KB)
📄
db_interface.c
(5.33 KB)
📄
db_trace.c
(3.3 KB)
📄
debug_monitor.c
(14.85 KB)
📄
disassem.c
(15.34 KB)
📄
dump_machdep.c
(2.19 KB)
📄
efirt_machdep.c
(7.31 KB)
📄
elf32_machdep.c
(7.31 KB)
📄
elf_machdep.c
(7.58 KB)
📄
exception.S
(6.02 KB)
📄
freebsd32_machdep.c
(11.11 KB)
📄
gdb_machdep.c
(3.21 KB)
📄
genassym.c
(3.45 KB)
📄
gic_v3.c
(35.72 KB)
📄
gic_v3_acpi.c
(10.84 KB)
📄
gic_v3_fdt.c
(9.3 KB)
📄
gic_v3_reg.h
(13.57 KB)
📄
gic_v3_var.h
(3.96 KB)
📄
gicv3_its.c
(51.37 KB)
📄
identcpu.c
(51.79 KB)
📄
in_cksum.c
(6.24 KB)
📄
locore.S
(18.17 KB)
📄
machdep.c
(33.05 KB)
📄
machdep_boot.c
(6.13 KB)
📄
mem.c
(3.48 KB)
📄
memcpy.S
(6.71 KB)
📄
memmove.S
(5.25 KB)
📄
minidump_machdep.c
(10.08 KB)
📄
mp_machdep.c
(19.43 KB)
📄
nexus.c
(14.39 KB)
📄
ofw_machdep.c
(1.9 KB)
📄
pmap.c
(190.66 KB)
📄
stack_machdep.c
(2.61 KB)
📄
support.S
(6.38 KB)
📄
swtch.S
(7.23 KB)
📄
sys_machdep.c
(1.66 KB)
📄
trap.c
(14.88 KB)
📄
uio_machdep.c
(4.22 KB)
📄
uma_machdep.c
(2.3 KB)
📄
undefined.c
(4.63 KB)
📄
unwind.c
(1.92 KB)
📄
vfp.c
(9.92 KB)
📄
vm_machdep.c
(7.35 KB)
Editing: cpufunc_asm.S
/*- * Copyright (c) 2014 Robin Randhawa * Copyright (c) 2015 The FreeBSD Foundation * All rights reserved. * * Portions of this software were developed by Andrew Turner * under sponsorship from the FreeBSD Foundation * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include <sys/errno.h> #include <machine/asm.h> #include <machine/param.h> #include "assym.inc" __FBSDID("$FreeBSD$"); /* * FIXME: * Need big.LITTLE awareness at some point. * Using arm64_p[id]cache_line_size may not be the best option. * Need better SMP awareness. */ .text .align 2 .Lpage_mask: .word PAGE_MASK /* * Macro to handle the cache. This takes the start address in x0, length * in x1. It will corrupt x0, x1, x2, x3, and x4. */ .macro cache_handle_range dcop = 0, ic = 0, icop = 0 .if \ic == 0 ldr x3, =dcache_line_size /* Load the D cache line size */ .else ldr x3, =idcache_line_size /* Load the I & D cache line size */ .endif ldr x3, [x3] sub x4, x3, #1 /* Get the address mask */ and x2, x0, x4 /* Get the low bits of the address */ add x1, x1, x2 /* Add these to the size */ bic x0, x0, x4 /* Clear the low bit of the address */ .if \ic != 0 mov x2, x0 /* Save the address */ mov x4, x1 /* Save the size */ .endif 1: dc \dcop, x0 add x0, x0, x3 /* Move to the next line */ subs x1, x1, x3 /* Reduce the size */ b.hi 1b /* Check if we are done */ dsb ish .if \ic != 0 2: ic \icop, x2 add x2, x2, x3 /* Move to the next line */ subs x4, x4, x3 /* Reduce the size */ b.hi 2b /* Check if we are done */ dsb ish isb .endif .endm ENTRY(arm64_nullop) ret END(arm64_nullop) /* * Generic functions to read/modify/write the internal coprocessor registers */ ENTRY(arm64_tlb_flushID) dsb ishst #ifdef SMP tlbi vmalle1is #else tlbi vmalle1 #endif dsb ish isb ret END(arm64_tlb_flushID) /* * void arm64_dcache_wb_range(vm_offset_t, vm_size_t) */ ENTRY(arm64_dcache_wb_range) cache_handle_range dcop = cvac ret END(arm64_dcache_wb_range) /* * void arm64_dcache_wbinv_range(vm_offset_t, vm_size_t) */ ENTRY(arm64_dcache_wbinv_range) cache_handle_range dcop = civac ret END(arm64_dcache_wbinv_range) /* * void arm64_dcache_inv_range(vm_offset_t, vm_size_t) * * Note, we must not invalidate everything. If the range is too big we * must use wb-inv of the entire cache. */ ENTRY(arm64_dcache_inv_range) cache_handle_range dcop = ivac ret END(arm64_dcache_inv_range) /* * void arm64_dic_idc_icache_sync_range(vm_offset_t, vm_size_t) * When the CTR_EL0.IDC bit is set cleaning to PoU becomes a dsb. * When the CTR_EL0.DIC bit is set icache invalidation becomes an isb. */ ENTRY(arm64_dic_idc_icache_sync_range) dsb ishst isb ret END(arm64_dic_idc_icache_sync_range) /* * void arm64_aliasing_icache_sync_range(vm_offset_t, vm_size_t) */ ENTRY(arm64_aliasing_icache_sync_range) /* * XXX Temporary solution - I-cache flush should be range based for * PIPT cache or IALLUIS for VIVT or VIPT caches */ /* cache_handle_range dcop = cvau, ic = 1, icop = ivau */ cache_handle_range dcop = cvau ic ialluis dsb ish isb ret END(arm64_aliasing_icache_sync_range) /* * int arm64_icache_sync_range_checked(vm_offset_t, vm_size_t) */ ENTRY(arm64_icache_sync_range_checked) adr x5, cache_maint_fault SET_FAULT_HANDLER(x5, x6) /* XXX: See comment in arm64_icache_sync_range */ cache_handle_range dcop = cvau ic ialluis dsb ish isb SET_FAULT_HANDLER(xzr, x6) mov x0, #0 ret END(arm64_icache_sync_range_checked) ENTRY(cache_maint_fault) SET_FAULT_HANDLER(xzr, x1) mov x0, #EFAULT ret END(cache_maint_fault)
Upload File
Create Folder