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autoconf.c
(3.3 KB)
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bcopy_page.S
(4.14 KB)
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bcopyinout.S
(3.35 KB)
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bcopyinout_xscale.S
(19.19 KB)
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blockio.S
(13.19 KB)
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bus_space_asm_generic.S
(5.43 KB)
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bus_space_base.c
(4.8 KB)
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bus_space_generic.c
(4.1 KB)
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busdma_machdep.c
(50.91 KB)
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copystr.S
(3.29 KB)
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cpu_asm-v6.S
(7.88 KB)
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cpufunc.c
(8.69 KB)
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cpufunc_asm.S
(2.53 KB)
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cpufunc_asm_arm11x6.S
(3.5 KB)
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cpufunc_asm_armv7.S
(1.82 KB)
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cpufunc_asm_pj4b.S
(3.47 KB)
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cpuinfo.c
(14.82 KB)
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db_disasm.c
(2.58 KB)
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db_interface.c
(7.03 KB)
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db_trace.c
(4.69 KB)
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debug_monitor.c
(24 KB)
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disassem.c
(20.16 KB)
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dump_machdep.c
(2.95 KB)
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elf_machdep.c
(8.8 KB)
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elf_note.S
(1.56 KB)
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exception.S
(14.21 KB)
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fiq.c
(4.69 KB)
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fiq_subr.S
(2.77 KB)
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fusu.S
(5.61 KB)
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gdb_machdep.c
(3.62 KB)
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genassym.c
(5.29 KB)
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generic_timer.c
(13.62 KB)
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gic.c
(32.64 KB)
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gic.h
(2.64 KB)
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gic_acpi.c
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gic_common.h
(4.19 KB)
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gic_fdt.c
(9.69 KB)
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hypervisor-stub.S
(2.61 KB)
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identcpu-v6.c
(10.16 KB)
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in_cksum.c
(4.23 KB)
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in_cksum_arm.S
(6.87 KB)
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locore-v6.S
(14.28 KB)
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locore.S
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machdep.c
(23.79 KB)
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machdep_boot.c
(12.48 KB)
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machdep_intr.c
(7.63 KB)
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machdep_kdb.c
(3.77 KB)
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machdep_ptrace.c
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mem.c
(5.03 KB)
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minidump_machdep.c
(8.77 KB)
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mp_machdep.c
(8.58 KB)
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mpcore_timer.c
(15.71 KB)
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mpcore_timervar.h
(2.03 KB)
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nexus.c
(11.33 KB)
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nexusvar.h
(1.54 KB)
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ofw_machdep.c
(2.28 KB)
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pl190.c
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pl310.c
(16.9 KB)
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platform.c
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platform_if.m
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platform_pl310_if.m
(2.44 KB)
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pmap-v6.c
(187.97 KB)
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pmu.c
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pmu.h
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pmu_fdt.c
(5.87 KB)
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ptrace_machdep.c
(1.89 KB)
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sc_machdep.c
(2.21 KB)
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setcpsr.S
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setstack.s
(3.16 KB)
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stack_machdep.c
(2.65 KB)
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stdatomic.c
(13.88 KB)
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support.S
(51.78 KB)
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swtch-v6.S
(13.07 KB)
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swtch.S
(4.68 KB)
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sys_machdep.c
(5.24 KB)
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syscall.c
(5.54 KB)
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trap-v6.c
(19.14 KB)
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uio_machdep.c
(3.95 KB)
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undefined.c
(9.07 KB)
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unwind.c
(16.62 KB)
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vfp.c
(9.1 KB)
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vm_machdep.c
(8.38 KB)
Editing: cpufunc_asm_pj4b.S
/*- * Copyright (C) 2011 MARVELL INTERNATIONAL LTD. * All rights reserved. * * Developed by Semihalf. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of MARVELL nor the names of contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include <machine/asm.h> __FBSDID("$FreeBSD$"); #include <machine/param.h> .Lpj4b_sf_ctrl_reg: .word 0xf1021820 ENTRY(pj4b_config) /* Set Auxiliary Debug Modes Control 0 register */ mrc p15, 1, r0, c15, c1, 0 /* ARMADAXP errata fix: ARM-CPU-6136 */ bic r0, r0, #(1 << 12) /* LDSTM first issue is single word */ orr r0, r0, #(1 << 22) /* DVM_WAKEUP disable */ mcr p15, 1, r0, c15, c1, 0 /* Set Auxiliary Debug Modes Control 1 register */ mrc p15, 1, r0, c15, c1, 1 /* ARMADAXP errata fix: ARM-CPU-6409 */ bic r0, r0, #(1 << 2) /* Disable static branch prediction */ orr r0, r0, #(1 << 5) /* STREX backoff disable */ orr r0, r0, #(1 << 8) /* Internal parity handling disable */ orr r0, r0, #(1 << 16) /* Disable data transfer for clean line */ mcr p15, 1, r0, c15, c1, 1 /* Set Auxiliary Function Modes Control 0 register */ mrc p15, 1, r0, c15, c2, 0 #if defined(SMP) orr r0, r0, #(1 << 1) /* SMP/nAMP enabled (coherency) */ #endif orr r0, r0, #(1 << 2) /* L1 parite enable */ orr r0, r0, #(1 << 8) /* Cache and TLB maintenance broadcast enable */ mcr p15, 1, r0, c15, c2, 0 /* Set Auxiliary Debug Modes Control 2 register */ mrc p15, 1, r0, c15, c1, 2 bic r0, r0, #(1 << 23) /* Enable fast LDR */ orr r0, r0, #(1 << 25) /* Intervention Interleave disable */ orr r0, r0, #(1 << 27) /* Critical word first sequencing disable */ orr r0, r0, #(1 << 29) /* Disable MO device read / write */ orr r0, r0, #(1 << 30) /* L1 cache strict round-robin replacement policy*/ orr r0, r0, #(1 << 31) /* Enable write evict */ mcr p15, 1, r0, c15, c1, 2 #if defined(SMP) /* Set SMP mode in Auxiliary Control Register */ mrc p15, 0, r0, c1, c0, 1 orr r0, r0, #(1 << 5) mcr p15, 0, r0, c1, c0, 1 #endif /* Load CPU number */ mrc p15, 0, r0, c0, c0, 5 and r0, r0, #0xf /* SF Enable and invalidate */ ldr r1, .Lpj4b_sf_ctrl_reg ldr r2, [r1, r0, lsl #8] orr r2, r2, #(1 << 0) bic r2, r2, #(1 << 8) str r2, [r1, r0, lsl #8] RET END(pj4b_config)
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