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📄 cvmip.h(5.88 KB)
📄 cvmx-abi.h(3.67 KB)
📄 cvmx-access-native.h(26.79 KB)
📄 cvmx-access.h(7.82 KB)
📄 cvmx-address.h(10.26 KB)
📄 cvmx-agl-defs.h(213.66 KB)
📄 cvmx-app-hotplug.c(27.64 KB)
📄 cvmx-app-hotplug.h(5.77 KB)
📄 cvmx-app-init-linux.c(14.29 KB)
📄 cvmx-app-init.c(22.54 KB)
📄 cvmx-app-init.h(19.32 KB)
📄 cvmx-asm.h(39.3 KB)
📄 cvmx-asx0-defs.h(5.19 KB)
📄 cvmx-asxx-defs.h(50.57 KB)
📄 cvmx-atomic.h(21.71 KB)
📄 cvmx-bootloader.h(5.64 KB)
📄 cvmx-bootmem.c(40.91 KB)
📄 cvmx-bootmem.h(18.88 KB)
📄 cvmx-ciu-defs.h(702.5 KB)
📄 cvmx-ciu2-defs.h(487.31 KB)
📄 cvmx-clock.c(4.48 KB)
📄 cvmx-clock.h(4.43 KB)
📄 cvmx-cmd-queue.c(11.84 KB)
📄 cvmx-cmd-queue.h(22 KB)
📄 cvmx-cn3010-evb-hs5.c(6.05 KB)
📄 cvmx-cn3010-evb-hs5.h(2.3 KB)
📄 cvmx-compactflash.c(12.8 KB)
📄 cvmx-compactflash.h(3.05 KB)
📄 cvmx-core.c(5.3 KB)
📄 cvmx-core.h(9.46 KB)
📄 cvmx-coremask.c(4.12 KB)
📄 cvmx-coremask.h(8.11 KB)
📄 cvmx-crypto.c(2.6 KB)
📄 cvmx-crypto.h(2.54 KB)
📄 cvmx-csr-enums.h(8.45 KB)
📄 cvmx-csr-typedefs.h(3.92 KB)
📄 cvmx-csr.h(11.46 KB)
📄 cvmx-dbg-defs.h(6.28 KB)
📄 cvmx-debug-handler.S(7.44 KB)
📄 cvmx-debug-remote.c(3.24 KB)
📄 cvmx-debug-uart.c(7.88 KB)
📄 cvmx-debug.c(55.98 KB)
📄 cvmx-debug.h(22.2 KB)
📄 cvmx-dfa-defs.h(383.08 KB)
📄 cvmx-dfa.c(3.7 KB)
📄 cvmx-dfa.h(34.87 KB)
📄 cvmx-dfm-defs.h(205.93 KB)
📄 cvmx-dma-engine.c(20.25 KB)
📄 cvmx-dma-engine.h(24.06 KB)
📄 cvmx-dpi-defs.h(107.61 KB)
📄 cvmx-ebt3000.c(3.82 KB)
📄 cvmx-ebt3000.h(2.25 KB)
📄 cvmx-endor-defs.h(311.42 KB)
📄 cvmx-eoi-defs.h(26.27 KB)
📄 cvmx-fau.h(20.31 KB)
📄 cvmx-flash.c(22.46 KB)
📄 cvmx-flash.h(3.8 KB)
📄 cvmx-fpa-defs.h(157.78 KB)
📄 cvmx-fpa.c(6.63 KB)
📄 cvmx-fpa.h(10.39 KB)
📄 cvmx-gmx.h(3.07 KB)
📄 cvmx-gmxx-defs.h(505.27 KB)
📄 cvmx-gpio-defs.h(36.89 KB)
📄 cvmx-gpio.h(5.48 KB)
📄 cvmx-helper-board.c(58 KB)
📄 cvmx-helper-board.h(7.82 KB)
📄 cvmx-helper-cfg.c(18.68 KB)
📄 cvmx-helper-cfg.h(8.1 KB)
📄 cvmx-helper-check-defines.h(4.1 KB)
📄 cvmx-helper-errata.c(11.91 KB)
📄 cvmx-helper-errata.h(3.24 KB)
📄 cvmx-helper-fpa.c(8.81 KB)
📄 cvmx-helper-fpa.h(3.21 KB)
📄 cvmx-helper-ilk.c(12.74 KB)
📄 cvmx-helper-ilk.h(3.58 KB)
📄 cvmx-helper-jtag.c(7.05 KB)
📄 cvmx-helper-jtag.h(3.91 KB)
📄 cvmx-helper-loop.c(4.35 KB)
📄 cvmx-helper-loop.h(2.78 KB)
📄 cvmx-helper-npi.c(5.72 KB)
📄 cvmx-helper-npi.h(2.82 KB)
📄 cvmx-helper-rgmii.c(19.12 KB)
📄 cvmx-helper-rgmii.h(4.5 KB)
📄 cvmx-helper-sgmii.c(27.09 KB)
📄 cvmx-helper-sgmii.h(4.3 KB)
📄 cvmx-helper-spi.c(8.4 KB)
📄 cvmx-helper-spi.h(3.68 KB)
📄 cvmx-helper-srio.c(11.58 KB)
📄 cvmx-helper-srio.h(3.6 KB)
📄 cvmx-helper-util.c(25.77 KB)
📄 cvmx-helper-util.h(9.88 KB)
📄 cvmx-helper-xaui.c(16.54 KB)
📄 cvmx-helper-xaui.h(4.29 KB)
📄 cvmx-helper.c(69.71 KB)
📄 cvmx-helper.h(12.7 KB)
📄 cvmx-hfa.c(5.04 KB)
📄 cvmx-hfa.h(10.3 KB)
📄 cvmx-higig.h(23.21 KB)
📄 cvmx-ilk-defs.h(170.31 KB)
📄 cvmx-ilk.c(45.16 KB)
📄 cvmx-ilk.h(5.89 KB)
📄 cvmx-interrupt-handler.S(5.87 KB)
📄 cvmx-interrupt.c(47.42 KB)
📄 cvmx-interrupt.h(8.07 KB)
📄 cvmx-iob-defs.h(89.11 KB)
📄 cvmx-iob1-defs.h(6.8 KB)
📄 cvmx-ipd-defs.h(186.51 KB)
📄 cvmx-ipd.c(12.88 KB)
📄 cvmx-ipd.h(6.3 KB)
📄 cvmx-ixf18201.c(12.8 KB)
📄 cvmx-ixf18201.h(3.54 KB)
📄 cvmx-key-defs.h(11 KB)
📄 cvmx-key.h(3.29 KB)
📄 cvmx-l2c-defs.h(353.27 KB)
📄 cvmx-l2c.c(52.95 KB)
📄 cvmx-l2c.h(19.72 KB)
📄 cvmx-l2d-defs.h(60.71 KB)
📄 cvmx-l2t-defs.h(50.68 KB)
📄 cvmx-led-defs.h(22.68 KB)
📄 cvmx-llm.c(36.51 KB)
📄 cvmx-llm.h(11.72 KB)
📄 cvmx-lmcx-defs.h(532.21 KB)
📄 cvmx-log-arc.S(5.67 KB)
📄 cvmx-log.c(18.26 KB)
📄 cvmx-log.h(4.95 KB)
📁 cvmx-malloc
📄 cvmx-malloc.h(7.2 KB)
📄 cvmx-mdio.h(15.99 KB)
📄 cvmx-mgmt-port.c(36.2 KB)
📄 cvmx-mgmt-port.h(7.23 KB)
📄 cvmx-mio-defs.h(454.14 KB)
📄 cvmx-mixx-defs.h(94.59 KB)
📄 cvmx-mpi-defs.h(33.42 KB)
📄 cvmx-nand.c(76.64 KB)
📄 cvmx-nand.h(26.85 KB)
📄 cvmx-ndf-defs.h(25.53 KB)
📄 cvmx-npei-defs.h(378.19 KB)
📄 cvmx-npi-defs.h(252.36 KB)
📄 cvmx-npi.h(4.69 KB)
📄 cvmx-packet.h(2.94 KB)
📄 cvmx-pci-defs.h(250.53 KB)
📄 cvmx-pci.h(2.37 KB)
📄 cvmx-pcie.c(63 KB)
📄 cvmx-pcie.h(10.08 KB)
📄 cvmx-pcieepx-defs.h(304.49 KB)
📄 cvmx-pciercx-defs.h(284.89 KB)
📄 cvmx-pcm-defs.h(12.34 KB)
📄 cvmx-pcmx-defs.h(46.12 KB)
📄 cvmx-pcsx-defs.h(71.23 KB)
📄 cvmx-pcsxx-defs.h(45.79 KB)
📄 cvmx-pemx-defs.h(68.97 KB)
📄 cvmx-pescx-defs.h(49.92 KB)
📄 cvmx-pexp-defs.h(97.89 KB)
📄 cvmx-pip-defs.h(315.91 KB)
📄 cvmx-pip.h(33.65 KB)
📄 cvmx-pko-defs.h(181.41 KB)
📄 cvmx-pko.c(32 KB)
📄 cvmx-pko.h(31.29 KB)
📄 cvmx-platform.h(7.45 KB)
📄 cvmx-pow-defs.h(93.02 KB)
📄 cvmx-pow.c(32.26 KB)
📄 cvmx-pow.h(100.93 KB)
📄 cvmx-power-throttle.c(7.25 KB)
📄 cvmx-power-throttle.h(3.85 KB)
📄 cvmx-profiler.c(7.81 KB)
📄 cvmx-profiler.h(3.15 KB)
📄 cvmx-qlm-tables.c(35.37 KB)
📄 cvmx-qlm.c(23.41 KB)
📄 cvmx-qlm.h(4.76 KB)
📄 cvmx-rad-defs.h(43.58 KB)
📄 cvmx-raid.c(4.71 KB)
📄 cvmx-raid.h(13.02 KB)
📄 cvmx-resources.config(7.66 KB)
📄 cvmx-rng.h(5.02 KB)
📄 cvmx-rnm-defs.h(13.03 KB)
📄 cvmx-rtc.h(4.21 KB)
📄 cvmx-rwlock.h(5.25 KB)
📄 cvmx-scratch.h(4.76 KB)
📄 cvmx-shared-linux-n32.ld(11.8 KB)
📄 cvmx-shared-linux-o32.ld(10.67 KB)
📄 cvmx-shared-linux.ld(11.77 KB)
📄 cvmx-shmem.c(18.89 KB)
📄 cvmx-shmem.h(4.11 KB)
📄 cvmx-sim-magic.h(5.59 KB)
📄 cvmx-sli-defs.h(312.94 KB)
📄 cvmx-smi-defs.h(4.09 KB)
📄 cvmx-smix-defs.h(21.71 KB)
📄 cvmx-spi.c(24.99 KB)
📄 cvmx-spi.h(10.22 KB)
📄 cvmx-spi4000.c(19.23 KB)
📄 cvmx-spinlock.h(11.73 KB)
📄 cvmx-spx0-defs.h(3.94 KB)
📄 cvmx-spxx-defs.h(62.44 KB)
📄 cvmx-srio.c(63.05 KB)
📄 cvmx-srio.h(26.68 KB)
📄 cvmx-sriomaintx-defs.h(222.52 KB)
📄 cvmx-sriox-defs.h(211.56 KB)
📄 cvmx-srxx-defs.h(14.41 KB)
📄 cvmx-sso-defs.h(87.33 KB)
📄 cvmx-stxx-defs.h(34.02 KB)
📄 cvmx-swap.h(4.11 KB)
📄 cvmx-sysinfo.c(8.78 KB)
📄 cvmx-sysinfo.h(6.45 KB)
📄 cvmx-thunder.c(9.22 KB)
📄 cvmx-thunder.h(4.54 KB)
📄 cvmx-tim-defs.h(58.36 KB)
📄 cvmx-tim.c(10.92 KB)
📄 cvmx-tim.h(12.1 KB)
📄 cvmx-tlb.c(10.12 KB)
📄 cvmx-tlb.h(5.07 KB)
📄 cvmx-tra-defs.h(4.59 KB)
📄 cvmx-tra.c(31.16 KB)
📄 cvmx-tra.h(34.28 KB)
📄 cvmx-trax-defs.h(197.09 KB)
📄 cvmx-twsi.c(16.25 KB)
📄 cvmx-twsi.h(10.22 KB)
📄 cvmx-uahcx-defs.h(181.38 KB)
📄 cvmx-uart.c(5.69 KB)
📄 cvmx-uart.h(4.58 KB)
📄 cvmx-uctlx-defs.h(50.26 KB)
📄 cvmx-usb.c(138.53 KB)
📄 cvmx-usb.h(46.67 KB)
📄 cvmx-usbcx-defs.h(259.23 KB)
📄 cvmx-usbd.c(36.09 KB)
📄 cvmx-usbd.h(9.82 KB)
📄 cvmx-usbnx-defs.h(136.12 KB)
📄 cvmx-utils.h(7.54 KB)
📄 cvmx-version.h(2.23 KB)
📄 cvmx-warn.c(2.75 KB)
📄 cvmx-warn.h(2.43 KB)
📄 cvmx-wqe.h(38.61 KB)
📄 cvmx-zip-defs.h(43.18 KB)
📄 cvmx-zip.c(7.37 KB)
📄 cvmx-zip.h(8.5 KB)
📄 cvmx-zone.c(4.7 KB)
📄 cvmx.h(3.5 KB)
📄 octeon-boot-info.h(8.08 KB)
📄 octeon-feature.c(4.71 KB)
📄 octeon-feature.h(11.94 KB)
📄 octeon-model.c(15.79 KB)
📄 octeon-model.h(16.53 KB)
📄 octeon-pci-console.c(19.73 KB)
📄 octeon-pci-console.h(5.18 KB)

Editing: cvmx-core.h

/***********************license start***************
 * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
 * reserved.
 *
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met:
 *
 *   * Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *
 *   * Redistributions in binary form must reproduce the above
 *     copyright notice, this list of conditions and the following
 *     disclaimer in the documentation and/or other materials provided
 *     with the distribution.

*   * Neither the name of Cavium Inc. nor the names of
 *     its contributors may be used to endorse or promote products
 *     derived from this software without specific prior written
 *     permission.

* This Software, including technical data, may be subject to U.S. export  control
 * laws, including the U.S. Export Administration Act and its  associated
 * regulations, and may be subject to export or import  regulations in other
 * countries.

* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
 ***********************license end**************************************/

/**
 * @file
 *
 * Module to support operations on core such as TLB config, etc.
 *
 * <hr>$Revision: 70030 $<hr>
 *
 */

#ifndef __CVMX_CORE_H__
#define __CVMX_CORE_H__

#ifdef	__cplusplus
extern "C" {
#endif

/**
 * The types of performance counters supported per cpu
 */
typedef enum
{
    CVMX_CORE_PERF_NONE      = 0,    /**< Turn off the performance counter */
    CVMX_CORE_PERF_CLK       = 1,    /**< Conditionally clocked cycles (as opposed to count/cvm_count which count even with no clocks) */
    CVMX_CORE_PERF_ISSUE     = 2,    /**< Instructions issued but not retired */
    CVMX_CORE_PERF_RET       = 3,    /**< Instructions retired */
    CVMX_CORE_PERF_NISSUE    = 4,    /**< Cycles no issue */
    CVMX_CORE_PERF_SISSUE    = 5,    /**< Cycles single issue */
    CVMX_CORE_PERF_DISSUE    = 6,    /**< Cycles dual issue */
    CVMX_CORE_PERF_IFI       = 7,    /**< Cycle ifetch issued (but not necessarily commit to pp_mem) */
    CVMX_CORE_PERF_BR        = 8,    /**< Branches retired */
    CVMX_CORE_PERF_BRMIS     = 9,    /**< Branch mispredicts */
    CVMX_CORE_PERF_J         = 10,   /**< Jumps retired */
    CVMX_CORE_PERF_JMIS      = 11,   /**< Jumps mispredicted */
    CVMX_CORE_PERF_REPLAY    = 12,   /**< Mem Replays */
    CVMX_CORE_PERF_IUNA      = 13,   /**< Cycles idle due to unaligned_replays */
    CVMX_CORE_PERF_TRAP      = 14,   /**< trap_6a signal */
    CVMX_CORE_PERF_UULOAD    = 16,   /**< Unexpected unaligned loads (REPUN=1) */
    CVMX_CORE_PERF_UUSTORE   = 17,   /**< Unexpected unaligned store (REPUN=1) */
    CVMX_CORE_PERF_ULOAD     = 18,   /**< Unaligned loads (REPUN=1 or USEUN=1) */
    CVMX_CORE_PERF_USTORE    = 19,   /**< Unaligned store (REPUN=1 or USEUN=1) */
    CVMX_CORE_PERF_EC        = 20,   /**< Exec clocks(must set CvmCtl[DISCE] for accurate timing) */
    CVMX_CORE_PERF_MC        = 21,   /**< Mul clocks(must set CvmCtl[DISCE] for accurate timing) */
    CVMX_CORE_PERF_CC        = 22,   /**< Crypto clocks(must set CvmCtl[DISCE] for accurate timing) */
    CVMX_CORE_PERF_CSRC      = 23,   /**< Issue_csr clocks(must set CvmCtl[DISCE] for accurate timing) */
    CVMX_CORE_PERF_CFETCH    = 24,   /**< Icache committed fetches (demand+prefetch) */
    CVMX_CORE_PERF_CPREF     = 25,   /**< Icache committed prefetches */
    CVMX_CORE_PERF_ICA       = 26,   /**< Icache aliases */
    CVMX_CORE_PERF_II        = 27,   /**< Icache invalidates */
    CVMX_CORE_PERF_IP        = 28,   /**< Icache parity error */
    CVMX_CORE_PERF_CIMISS    = 29,   /**< Cycles idle due to imiss (must set CvmCtl[DISCE] for accurate timing) */
    CVMX_CORE_PERF_WBUF      = 32,   /**< Number of write buffer entries created */
    CVMX_CORE_PERF_WDAT      = 33,   /**< Number of write buffer data cycles used (may need to set CvmCtl[DISCE] for accurate counts) */
    CVMX_CORE_PERF_WBUFLD    = 34,   /**< Number of write buffer entries forced out by loads */
    CVMX_CORE_PERF_WBUFFL    = 35,   /**< Number of cycles that there was no available write buffer entry (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) */
    CVMX_CORE_PERF_WBUFTR    = 36,   /**< Number of stores that found no available write buffer entries */
    CVMX_CORE_PERF_BADD      = 37,   /**< Number of address bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) */
    CVMX_CORE_PERF_BADDL2    = 38,   /**< Number of address bus cycles not reflected (i.e. destined for L2) (may need to set CvmCtl[DISCE] for accurate counts) */
    CVMX_CORE_PERF_BFILL     = 39,   /**< Number of fill bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) */
    CVMX_CORE_PERF_DDIDS     = 40,   /**< Number of Dstream DIDs created */
    CVMX_CORE_PERF_IDIDS     = 41,   /**< Number of Istream DIDs created */
    CVMX_CORE_PERF_DIDNA     = 42,   /**< Number of cycles that no DIDs were available (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) */
    CVMX_CORE_PERF_LDS       = 43,   /**< Number of load issues */
    CVMX_CORE_PERF_LMLDS     = 44,   /**< Number of local memory load */
    CVMX_CORE_PERF_IOLDS     = 45,   /**< Number of I/O load issues */
    CVMX_CORE_PERF_DMLDS     = 46,   /**< Number of loads that were not prefetches and missed in the cache */
    CVMX_CORE_PERF_STS       = 48,   /**< Number of store issues */
    CVMX_CORE_PERF_LMSTS     = 49,   /**< Number of local memory store issues */
    CVMX_CORE_PERF_IOSTS     = 50,   /**< Number of I/O store issues */
    CVMX_CORE_PERF_IOBDMA    = 51,   /**< Number of IOBDMAs */
    CVMX_CORE_PERF_DTLB      = 53,   /**< Number of dstream TLB refill, invalid, or modified exceptions */
    CVMX_CORE_PERF_DTLBAD    = 54,   /**< Number of dstream TLB address errors */
    CVMX_CORE_PERF_ITLB      = 55,   /**< Number of istream TLB refill, invalid, or address error exceptions */
    CVMX_CORE_PERF_SYNC      = 56,   /**< Number of SYNC stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */
    CVMX_CORE_PERF_SYNCIOB   = 57,   /**< Number of SYNCIOBDMA stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */
    CVMX_CORE_PERF_SYNCW     = 58,   /**< Number of SYNCWs */
    /* Added in CN63XX */
    CVMX_CORE_PERF_ERETMIS   = 64,   /**< D/eret mispredicts */
    CVMX_CORE_PERF_LIKMIS    = 65,   /**< Branch likely mispredicts */
    CVMX_CORE_PERF_HAZTR     = 66,   /**< Hazard traps due to *MTC0 to CvmCtl, Perf counter control, EntryHi, or CvmMemCtl registers */
    CVMX_CORE_PERF_MAX               /**< This not a counter, just a marker for the highest number */
} cvmx_core_perf_t;

/**
 * Bit description of the COP0 counter control register
 */
typedef union
{
    uint32_t u32;
    struct
    {
#ifdef __BIG_ENDIAN_BITFIELD
        uint32_t m              : 1; /**< Set to 1 for sel 0 and 0 for sel 2, indicating there are two performance counters */
        uint32_t w              : 1; /**< Set to 1 indicating counters are 64 bit */
        uint32_t reserved_11_29 :15;
        cvmx_core_perf_t event  :10; /**< Selects the event to be counted by the corresponding Counter Register */
        uint32_t ie             : 1; /**< Interrupt Enable */
        uint32_t u              : 1; /**< Count in user mode */
        uint32_t s              : 1; /**< Count in supervisor mode */
        uint32_t k              : 1; /**< Count in kernel mode */
        uint32_t ex             : 1; /**< Count in exception context */
#else
	uint32_t ex             : 1;
        uint32_t k              : 1;
        uint32_t s              : 1;
        uint32_t u              : 1;
        uint32_t ie             : 1;
        uint32_t event          :10;
        uint32_t reserved_11_29 :15;
        uint32_t w              : 1;
        uint32_t m              : 1;
#endif
    } s;
} cvmx_core_perf_control_t;

typedef enum {
    CVMX_TLB_PAGEMASK_4K   = 0x3     << 11,
    CVMX_TLB_PAGEMASK_16K  = 0xF     << 11,
    CVMX_TLB_PAGEMASK_64K  = 0x3F    << 11,
    CVMX_TLB_PAGEMASK_256K = 0xFF    << 11,
    CVMX_TLB_PAGEMASK_1M   = 0x3FF   << 11,
    CVMX_TLB_PAGEMASK_4M   = 0xFFF   << 11,
    CVMX_TLB_PAGEMASK_16M  = 0x3FFF  << 11,
    CVMX_TLB_PAGEMASK_64M  = 0xFFFF  << 11,
    CVMX_TLB_PAGEMASK_256M = 0x3FFFF << 11,
} cvmx_tlb_pagemask_t;

int cvmx_core_add_wired_tlb_entry(uint64_t hi, uint64_t lo0, uint64_t lo1, cvmx_tlb_pagemask_t page_mask);

int cvmx_core_add_fixed_tlb_mapping(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask);
int cvmx_core_add_fixed_tlb_mapping_bits(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask);

/**
 * Return number of TLB entries.
 */
int cvmx_core_get_tlb_entries(void);
#ifdef	__cplusplus
}
#endif

#endif /* __CVMX_CORE_H__ */

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