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📄 cvmip.h(5.88 KB)
📄 cvmx-abi.h(3.67 KB)
📄 cvmx-access-native.h(26.79 KB)
📄 cvmx-access.h(7.82 KB)
📄 cvmx-address.h(10.26 KB)
📄 cvmx-agl-defs.h(213.66 KB)
📄 cvmx-app-hotplug.c(27.64 KB)
📄 cvmx-app-hotplug.h(5.77 KB)
📄 cvmx-app-init-linux.c(14.29 KB)
📄 cvmx-app-init.c(22.54 KB)
📄 cvmx-app-init.h(19.32 KB)
📄 cvmx-asm.h(39.3 KB)
📄 cvmx-asx0-defs.h(5.19 KB)
📄 cvmx-asxx-defs.h(50.57 KB)
📄 cvmx-atomic.h(21.71 KB)
📄 cvmx-bootloader.h(5.64 KB)
📄 cvmx-bootmem.c(40.91 KB)
📄 cvmx-bootmem.h(18.88 KB)
📄 cvmx-ciu-defs.h(702.5 KB)
📄 cvmx-ciu2-defs.h(487.31 KB)
📄 cvmx-clock.c(4.48 KB)
📄 cvmx-clock.h(4.43 KB)
📄 cvmx-cmd-queue.c(11.84 KB)
📄 cvmx-cmd-queue.h(22 KB)
📄 cvmx-cn3010-evb-hs5.c(6.05 KB)
📄 cvmx-cn3010-evb-hs5.h(2.3 KB)
📄 cvmx-compactflash.c(12.8 KB)
📄 cvmx-compactflash.h(3.05 KB)
📄 cvmx-core.c(5.3 KB)
📄 cvmx-core.h(9.46 KB)
📄 cvmx-coremask.c(4.12 KB)
📄 cvmx-coremask.h(8.11 KB)
📄 cvmx-crypto.c(2.6 KB)
📄 cvmx-crypto.h(2.54 KB)
📄 cvmx-csr-enums.h(8.45 KB)
📄 cvmx-csr-typedefs.h(3.92 KB)
📄 cvmx-csr.h(11.46 KB)
📄 cvmx-dbg-defs.h(6.28 KB)
📄 cvmx-debug-handler.S(7.44 KB)
📄 cvmx-debug-remote.c(3.24 KB)
📄 cvmx-debug-uart.c(7.88 KB)
📄 cvmx-debug.c(55.98 KB)
📄 cvmx-debug.h(22.2 KB)
📄 cvmx-dfa-defs.h(383.08 KB)
📄 cvmx-dfa.c(3.7 KB)
📄 cvmx-dfa.h(34.87 KB)
📄 cvmx-dfm-defs.h(205.93 KB)
📄 cvmx-dma-engine.c(20.25 KB)
📄 cvmx-dma-engine.h(24.06 KB)
📄 cvmx-dpi-defs.h(107.61 KB)
📄 cvmx-ebt3000.c(3.82 KB)
📄 cvmx-ebt3000.h(2.25 KB)
📄 cvmx-endor-defs.h(311.42 KB)
📄 cvmx-eoi-defs.h(26.27 KB)
📄 cvmx-fau.h(20.31 KB)
📄 cvmx-flash.c(22.46 KB)
📄 cvmx-flash.h(3.8 KB)
📄 cvmx-fpa-defs.h(157.78 KB)
📄 cvmx-fpa.c(6.63 KB)
📄 cvmx-fpa.h(10.39 KB)
📄 cvmx-gmx.h(3.07 KB)
📄 cvmx-gmxx-defs.h(505.27 KB)
📄 cvmx-gpio-defs.h(36.89 KB)
📄 cvmx-gpio.h(5.48 KB)
📄 cvmx-helper-board.c(58 KB)
📄 cvmx-helper-board.h(7.82 KB)
📄 cvmx-helper-cfg.c(18.68 KB)
📄 cvmx-helper-cfg.h(8.1 KB)
📄 cvmx-helper-check-defines.h(4.1 KB)
📄 cvmx-helper-errata.c(11.91 KB)
📄 cvmx-helper-errata.h(3.24 KB)
📄 cvmx-helper-fpa.c(8.81 KB)
📄 cvmx-helper-fpa.h(3.21 KB)
📄 cvmx-helper-ilk.c(12.74 KB)
📄 cvmx-helper-ilk.h(3.58 KB)
📄 cvmx-helper-jtag.c(7.05 KB)
📄 cvmx-helper-jtag.h(3.91 KB)
📄 cvmx-helper-loop.c(4.35 KB)
📄 cvmx-helper-loop.h(2.78 KB)
📄 cvmx-helper-npi.c(5.72 KB)
📄 cvmx-helper-npi.h(2.82 KB)
📄 cvmx-helper-rgmii.c(19.12 KB)
📄 cvmx-helper-rgmii.h(4.5 KB)
📄 cvmx-helper-sgmii.c(27.09 KB)
📄 cvmx-helper-sgmii.h(4.3 KB)
📄 cvmx-helper-spi.c(8.4 KB)
📄 cvmx-helper-spi.h(3.68 KB)
📄 cvmx-helper-srio.c(11.58 KB)
📄 cvmx-helper-srio.h(3.6 KB)
📄 cvmx-helper-util.c(25.77 KB)
📄 cvmx-helper-util.h(9.88 KB)
📄 cvmx-helper-xaui.c(16.54 KB)
📄 cvmx-helper-xaui.h(4.29 KB)
📄 cvmx-helper.c(69.71 KB)
📄 cvmx-helper.h(12.7 KB)
📄 cvmx-hfa.c(5.04 KB)
📄 cvmx-hfa.h(10.3 KB)
📄 cvmx-higig.h(23.21 KB)
📄 cvmx-ilk-defs.h(170.31 KB)
📄 cvmx-ilk.c(45.16 KB)
📄 cvmx-ilk.h(5.89 KB)
📄 cvmx-interrupt-handler.S(5.87 KB)
📄 cvmx-interrupt.c(47.42 KB)
📄 cvmx-interrupt.h(8.07 KB)
📄 cvmx-iob-defs.h(89.11 KB)
📄 cvmx-iob1-defs.h(6.8 KB)
📄 cvmx-ipd-defs.h(186.51 KB)
📄 cvmx-ipd.c(12.88 KB)
📄 cvmx-ipd.h(6.3 KB)
📄 cvmx-ixf18201.c(12.8 KB)
📄 cvmx-ixf18201.h(3.54 KB)
📄 cvmx-key-defs.h(11 KB)
📄 cvmx-key.h(3.29 KB)
📄 cvmx-l2c-defs.h(353.27 KB)
📄 cvmx-l2c.c(52.95 KB)
📄 cvmx-l2c.h(19.72 KB)
📄 cvmx-l2d-defs.h(60.71 KB)
📄 cvmx-l2t-defs.h(50.68 KB)
📄 cvmx-led-defs.h(22.68 KB)
📄 cvmx-llm.c(36.51 KB)
📄 cvmx-llm.h(11.72 KB)
📄 cvmx-lmcx-defs.h(532.21 KB)
📄 cvmx-log-arc.S(5.67 KB)
📄 cvmx-log.c(18.26 KB)
📄 cvmx-log.h(4.95 KB)
📁 cvmx-malloc
📄 cvmx-malloc.h(7.2 KB)
📄 cvmx-mdio.h(15.99 KB)
📄 cvmx-mgmt-port.c(36.2 KB)
📄 cvmx-mgmt-port.h(7.23 KB)
📄 cvmx-mio-defs.h(454.14 KB)
📄 cvmx-mixx-defs.h(94.59 KB)
📄 cvmx-mpi-defs.h(33.42 KB)
📄 cvmx-nand.c(76.64 KB)
📄 cvmx-nand.h(26.85 KB)
📄 cvmx-ndf-defs.h(25.53 KB)
📄 cvmx-npei-defs.h(378.19 KB)
📄 cvmx-npi-defs.h(252.36 KB)
📄 cvmx-npi.h(4.69 KB)
📄 cvmx-packet.h(2.94 KB)
📄 cvmx-pci-defs.h(250.53 KB)
📄 cvmx-pci.h(2.37 KB)
📄 cvmx-pcie.c(63 KB)
📄 cvmx-pcie.h(10.08 KB)
📄 cvmx-pcieepx-defs.h(304.49 KB)
📄 cvmx-pciercx-defs.h(284.89 KB)
📄 cvmx-pcm-defs.h(12.34 KB)
📄 cvmx-pcmx-defs.h(46.12 KB)
📄 cvmx-pcsx-defs.h(71.23 KB)
📄 cvmx-pcsxx-defs.h(45.79 KB)
📄 cvmx-pemx-defs.h(68.97 KB)
📄 cvmx-pescx-defs.h(49.92 KB)
📄 cvmx-pexp-defs.h(97.89 KB)
📄 cvmx-pip-defs.h(315.91 KB)
📄 cvmx-pip.h(33.65 KB)
📄 cvmx-pko-defs.h(181.41 KB)
📄 cvmx-pko.c(32 KB)
📄 cvmx-pko.h(31.29 KB)
📄 cvmx-platform.h(7.45 KB)
📄 cvmx-pow-defs.h(93.02 KB)
📄 cvmx-pow.c(32.26 KB)
📄 cvmx-pow.h(100.93 KB)
📄 cvmx-power-throttle.c(7.25 KB)
📄 cvmx-power-throttle.h(3.85 KB)
📄 cvmx-profiler.c(7.81 KB)
📄 cvmx-profiler.h(3.15 KB)
📄 cvmx-qlm-tables.c(35.37 KB)
📄 cvmx-qlm.c(23.41 KB)
📄 cvmx-qlm.h(4.76 KB)
📄 cvmx-rad-defs.h(43.58 KB)
📄 cvmx-raid.c(4.71 KB)
📄 cvmx-raid.h(13.02 KB)
📄 cvmx-resources.config(7.66 KB)
📄 cvmx-rng.h(5.02 KB)
📄 cvmx-rnm-defs.h(13.03 KB)
📄 cvmx-rtc.h(4.21 KB)
📄 cvmx-rwlock.h(5.25 KB)
📄 cvmx-scratch.h(4.76 KB)
📄 cvmx-shared-linux-n32.ld(11.8 KB)
📄 cvmx-shared-linux-o32.ld(10.67 KB)
📄 cvmx-shared-linux.ld(11.77 KB)
📄 cvmx-shmem.c(18.89 KB)
📄 cvmx-shmem.h(4.11 KB)
📄 cvmx-sim-magic.h(5.59 KB)
📄 cvmx-sli-defs.h(312.94 KB)
📄 cvmx-smi-defs.h(4.09 KB)
📄 cvmx-smix-defs.h(21.71 KB)
📄 cvmx-spi.c(24.99 KB)
📄 cvmx-spi.h(10.22 KB)
📄 cvmx-spi4000.c(19.23 KB)
📄 cvmx-spinlock.h(11.73 KB)
📄 cvmx-spx0-defs.h(3.94 KB)
📄 cvmx-spxx-defs.h(62.44 KB)
📄 cvmx-srio.c(63.05 KB)
📄 cvmx-srio.h(26.68 KB)
📄 cvmx-sriomaintx-defs.h(222.52 KB)
📄 cvmx-sriox-defs.h(211.56 KB)
📄 cvmx-srxx-defs.h(14.41 KB)
📄 cvmx-sso-defs.h(87.33 KB)
📄 cvmx-stxx-defs.h(34.02 KB)
📄 cvmx-swap.h(4.11 KB)
📄 cvmx-sysinfo.c(8.78 KB)
📄 cvmx-sysinfo.h(6.45 KB)
📄 cvmx-thunder.c(9.22 KB)
📄 cvmx-thunder.h(4.54 KB)
📄 cvmx-tim-defs.h(58.36 KB)
📄 cvmx-tim.c(10.92 KB)
📄 cvmx-tim.h(12.1 KB)
📄 cvmx-tlb.c(10.12 KB)
📄 cvmx-tlb.h(5.07 KB)
📄 cvmx-tra-defs.h(4.59 KB)
📄 cvmx-tra.c(31.16 KB)
📄 cvmx-tra.h(34.28 KB)
📄 cvmx-trax-defs.h(197.09 KB)
📄 cvmx-twsi.c(16.25 KB)
📄 cvmx-twsi.h(10.22 KB)
📄 cvmx-uahcx-defs.h(181.38 KB)
📄 cvmx-uart.c(5.69 KB)
📄 cvmx-uart.h(4.58 KB)
📄 cvmx-uctlx-defs.h(50.26 KB)
📄 cvmx-usb.c(138.53 KB)
📄 cvmx-usb.h(46.67 KB)
📄 cvmx-usbcx-defs.h(259.23 KB)
📄 cvmx-usbd.c(36.09 KB)
📄 cvmx-usbd.h(9.82 KB)
📄 cvmx-usbnx-defs.h(136.12 KB)
📄 cvmx-utils.h(7.54 KB)
📄 cvmx-version.h(2.23 KB)
📄 cvmx-warn.c(2.75 KB)
📄 cvmx-warn.h(2.43 KB)
📄 cvmx-wqe.h(38.61 KB)
📄 cvmx-zip-defs.h(43.18 KB)
📄 cvmx-zip.c(7.37 KB)
📄 cvmx-zip.h(8.5 KB)
📄 cvmx-zone.c(4.7 KB)
📄 cvmx.h(3.5 KB)
📄 octeon-boot-info.h(8.08 KB)
📄 octeon-feature.c(4.71 KB)
📄 octeon-feature.h(11.94 KB)
📄 octeon-model.c(15.79 KB)
📄 octeon-model.h(16.53 KB)
📄 octeon-pci-console.c(19.73 KB)
📄 octeon-pci-console.h(5.18 KB)

Editing: cvmx-l2d-defs.h

/***********************license start***************
 * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
 * reserved.
 *
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met:
 *
 *   * Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *
 *   * Redistributions in binary form must reproduce the above
 *     copyright notice, this list of conditions and the following
 *     disclaimer in the documentation and/or other materials provided
 *     with the distribution.

*   * Neither the name of Cavium Inc. nor the names of
 *     its contributors may be used to endorse or promote products
 *     derived from this software without specific prior written
 *     permission.

* This Software, including technical data, may be subject to U.S. export  control
 * laws, including the U.S. Export Administration Act and its  associated
 * regulations, and may be subject to export or import  regulations in other
 * countries.

* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
 ***********************license end**************************************/

/**
 * cvmx-l2d-defs.h
 *
 * Configuration and status register (CSR) type definitions for
 * Octeon l2d.
 *
 * This file is auto generated. Do not edit.
 *
 * <hr>$Revision$<hr>
 *
 */
#ifndef __CVMX_L2D_DEFS_H__
#define __CVMX_L2D_DEFS_H__

#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_L2D_BST0 CVMX_L2D_BST0_FUNC()
static inline uint64_t CVMX_L2D_BST0_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
		cvmx_warn("CVMX_L2D_BST0 not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001180080000780ull);
}
#else
#define CVMX_L2D_BST0 (CVMX_ADD_IO_SEG(0x0001180080000780ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_L2D_BST1 CVMX_L2D_BST1_FUNC()
static inline uint64_t CVMX_L2D_BST1_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
		cvmx_warn("CVMX_L2D_BST1 not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001180080000788ull);
}
#else
#define CVMX_L2D_BST1 (CVMX_ADD_IO_SEG(0x0001180080000788ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_L2D_BST2 CVMX_L2D_BST2_FUNC()
static inline uint64_t CVMX_L2D_BST2_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
		cvmx_warn("CVMX_L2D_BST2 not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001180080000790ull);
}
#else
#define CVMX_L2D_BST2 (CVMX_ADD_IO_SEG(0x0001180080000790ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_L2D_BST3 CVMX_L2D_BST3_FUNC()
static inline uint64_t CVMX_L2D_BST3_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
		cvmx_warn("CVMX_L2D_BST3 not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001180080000798ull);
}
#else
#define CVMX_L2D_BST3 (CVMX_ADD_IO_SEG(0x0001180080000798ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_L2D_ERR CVMX_L2D_ERR_FUNC()
static inline uint64_t CVMX_L2D_ERR_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
		cvmx_warn("CVMX_L2D_ERR not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001180080000010ull);
}
#else
#define CVMX_L2D_ERR (CVMX_ADD_IO_SEG(0x0001180080000010ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_L2D_FADR CVMX_L2D_FADR_FUNC()
static inline uint64_t CVMX_L2D_FADR_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
		cvmx_warn("CVMX_L2D_FADR not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001180080000018ull);
}
#else
#define CVMX_L2D_FADR (CVMX_ADD_IO_SEG(0x0001180080000018ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_L2D_FSYN0 CVMX_L2D_FSYN0_FUNC()
static inline uint64_t CVMX_L2D_FSYN0_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
		cvmx_warn("CVMX_L2D_FSYN0 not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001180080000020ull);
}
#else
#define CVMX_L2D_FSYN0 (CVMX_ADD_IO_SEG(0x0001180080000020ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_L2D_FSYN1 CVMX_L2D_FSYN1_FUNC()
static inline uint64_t CVMX_L2D_FSYN1_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
		cvmx_warn("CVMX_L2D_FSYN1 not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001180080000028ull);
}
#else
#define CVMX_L2D_FSYN1 (CVMX_ADD_IO_SEG(0x0001180080000028ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_L2D_FUS0 CVMX_L2D_FUS0_FUNC()
static inline uint64_t CVMX_L2D_FUS0_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
		cvmx_warn("CVMX_L2D_FUS0 not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x00011800800007A0ull);
}
#else
#define CVMX_L2D_FUS0 (CVMX_ADD_IO_SEG(0x00011800800007A0ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_L2D_FUS1 CVMX_L2D_FUS1_FUNC()
static inline uint64_t CVMX_L2D_FUS1_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
		cvmx_warn("CVMX_L2D_FUS1 not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x00011800800007A8ull);
}
#else
#define CVMX_L2D_FUS1 (CVMX_ADD_IO_SEG(0x00011800800007A8ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_L2D_FUS2 CVMX_L2D_FUS2_FUNC()
static inline uint64_t CVMX_L2D_FUS2_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
		cvmx_warn("CVMX_L2D_FUS2 not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x00011800800007B0ull);
}
#else
#define CVMX_L2D_FUS2 (CVMX_ADD_IO_SEG(0x00011800800007B0ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_L2D_FUS3 CVMX_L2D_FUS3_FUNC()
static inline uint64_t CVMX_L2D_FUS3_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
		cvmx_warn("CVMX_L2D_FUS3 not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x00011800800007B8ull);
}
#else
#define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull))
#endif

/**
 * cvmx_l2d_bst0
 *
 * L2D_BST0 = L2C Data Store QUAD0 BIST Status Register
 *
 */
union cvmx_l2d_bst0 {
	uint64_t u64;
	struct cvmx_l2d_bst0_s {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_35_63               : 29;
	uint64_t ftl                          : 1;  /**< L2C Data Store Fatal Defect(across all QUADs)
                                                         2 or more columns were detected bad across all
                                                         QUADs[0-3]. Please refer to individual quad failures
                                                         for bad column = 0x7e to determine which QUAD was in
                                                         error. */
	uint64_t q0stat                       : 34; /**< Bist Results for QUAD0
                                                         Failure \#1 Status
                                                           [16:14] bad bank
                                                           [13:7] bad high column
                                                           [6:0] bad low column
                                                         Failure \#2 Status
                                                           [33:31] bad bank
                                                           [30:24] bad high column
                                                           [23:17] bad low column
                                                         NOTES: For bad high/low column reporting:
                                                            0x7f:   No failure
                                                            0x7e:   Fatal Defect: 2 or more bad columns
                                                            0-0x45: Bad column
                                                         NOTE: If there are less than 2 failures then the
                                                            bad bank will be 0x7. */
#else
	uint64_t q0stat                       : 34;
	uint64_t ftl                          : 1;
	uint64_t reserved_35_63               : 29;
#endif
	} s;
	struct cvmx_l2d_bst0_s                cn30xx;
	struct cvmx_l2d_bst0_s                cn31xx;
	struct cvmx_l2d_bst0_s                cn38xx;
	struct cvmx_l2d_bst0_s                cn38xxp2;
	struct cvmx_l2d_bst0_s                cn50xx;
	struct cvmx_l2d_bst0_s                cn52xx;
	struct cvmx_l2d_bst0_s                cn52xxp1;
	struct cvmx_l2d_bst0_s                cn56xx;
	struct cvmx_l2d_bst0_s                cn56xxp1;
	struct cvmx_l2d_bst0_s                cn58xx;
	struct cvmx_l2d_bst0_s                cn58xxp1;
};
typedef union cvmx_l2d_bst0 cvmx_l2d_bst0_t;

/**
 * cvmx_l2d_bst1
 *
 * L2D_BST1 = L2C Data Store QUAD1 BIST Status Register
 *
 */
union cvmx_l2d_bst1 {
	uint64_t u64;
	struct cvmx_l2d_bst1_s {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_34_63               : 30;
	uint64_t q1stat                       : 34; /**< Bist Results for QUAD1
                                                         Failure \#1 Status
                                                            [16:14] bad bank
                                                            [13:7] bad high column
                                                            [6:0] bad low column
                                                          Failure \#2 Status
                                                            [33:31] bad bank
                                                            [30:24] bad high column
                                                            [23:17] bad low column
                                                          NOTES: For bad high/low column reporting:
                                                             0x7f:   No failure
                                                             0x7e:   Fatal Defect: 2 or more bad columns
                                                             0-0x45: Bad column
                                                          NOTE: If there are less than 2 failures then the
                                                             bad bank will be 0x7. */
#else
	uint64_t q1stat                       : 34;
	uint64_t reserved_34_63               : 30;
#endif
	} s;
	struct cvmx_l2d_bst1_s                cn30xx;
	struct cvmx_l2d_bst1_s                cn31xx;
	struct cvmx_l2d_bst1_s                cn38xx;
	struct cvmx_l2d_bst1_s                cn38xxp2;
	struct cvmx_l2d_bst1_s                cn50xx;
	struct cvmx_l2d_bst1_s                cn52xx;
	struct cvmx_l2d_bst1_s                cn52xxp1;
	struct cvmx_l2d_bst1_s                cn56xx;
	struct cvmx_l2d_bst1_s                cn56xxp1;
	struct cvmx_l2d_bst1_s                cn58xx;
	struct cvmx_l2d_bst1_s                cn58xxp1;
};
typedef union cvmx_l2d_bst1 cvmx_l2d_bst1_t;

/**
 * cvmx_l2d_bst2
 *
 * L2D_BST2 = L2C Data Store QUAD2 BIST Status Register
 *
 */
union cvmx_l2d_bst2 {
	uint64_t u64;
	struct cvmx_l2d_bst2_s {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_34_63               : 30;
	uint64_t q2stat                       : 34; /**< Bist Results for QUAD2
                                                         Failure \#1 Status
                                                            [16:14] bad bank
                                                            [13:7] bad high column
                                                            [6:0] bad low column
                                                          Failure \#2 Status
                                                            [33:31] bad bank
                                                            [30:24] bad high column
                                                            [23:17] bad low column
                                                          NOTES: For bad high/low column reporting:
                                                             0x7f:   No failure
                                                             0x7e:   Fatal Defect: 2 or more bad columns
                                                             0-0x45: Bad column
                                                          NOTE: If there are less than 2 failures then the
                                                             bad bank will be 0x7. */
#else
	uint64_t q2stat                       : 34;
	uint64_t reserved_34_63               : 30;
#endif
	} s;
	struct cvmx_l2d_bst2_s                cn30xx;
	struct cvmx_l2d_bst2_s                cn31xx;
	struct cvmx_l2d_bst2_s                cn38xx;
	struct cvmx_l2d_bst2_s                cn38xxp2;
	struct cvmx_l2d_bst2_s                cn50xx;
	struct cvmx_l2d_bst2_s                cn52xx;
	struct cvmx_l2d_bst2_s                cn52xxp1;
	struct cvmx_l2d_bst2_s                cn56xx;
	struct cvmx_l2d_bst2_s                cn56xxp1;
	struct cvmx_l2d_bst2_s                cn58xx;
	struct cvmx_l2d_bst2_s                cn58xxp1;
};
typedef union cvmx_l2d_bst2 cvmx_l2d_bst2_t;

/**
 * cvmx_l2d_bst3
 *
 * L2D_BST3 = L2C Data Store QUAD3 BIST Status Register
 *
 */
union cvmx_l2d_bst3 {
	uint64_t u64;
	struct cvmx_l2d_bst3_s {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_34_63               : 30;
	uint64_t q3stat                       : 34; /**< Bist Results for QUAD3
                                                         Failure \#1 Status
                                                            [16:14] bad bank
                                                            [13:7] bad high column
                                                            [6:0] bad low column
                                                          Failure \#2 Status
                                                            [33:31] bad bank
                                                            [30:24] bad high column
                                                            [23:17] bad low column
                                                          NOTES: For bad high/low column reporting:
                                                             0x7f:   No failure
                                                             0x7e:   Fatal Defect: 2 or more bad columns
                                                             0-0x45: Bad column
                                                          NOTE: If there are less than 2 failures then the
                                                             bad bank will be 0x7. */
#else
	uint64_t q3stat                       : 34;
	uint64_t reserved_34_63               : 30;
#endif
	} s;
	struct cvmx_l2d_bst3_s                cn30xx;
	struct cvmx_l2d_bst3_s                cn31xx;
	struct cvmx_l2d_bst3_s                cn38xx;
	struct cvmx_l2d_bst3_s                cn38xxp2;
	struct cvmx_l2d_bst3_s                cn50xx;
	struct cvmx_l2d_bst3_s                cn52xx;
	struct cvmx_l2d_bst3_s                cn52xxp1;
	struct cvmx_l2d_bst3_s                cn56xx;
	struct cvmx_l2d_bst3_s                cn56xxp1;
	struct cvmx_l2d_bst3_s                cn58xx;
	struct cvmx_l2d_bst3_s                cn58xxp1;
};
typedef union cvmx_l2d_bst3 cvmx_l2d_bst3_t;

/**
 * cvmx_l2d_err
 *
 * L2D_ERR = L2 Data Errors
 *
 * Description: L2 Data ECC SEC/DED Errors and Interrupt Enable
 */
union cvmx_l2d_err {
	uint64_t u64;
	struct cvmx_l2d_err_s {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_6_63                : 58;
	uint64_t bmhclsel                     : 1;  /**< L2 Bit Map Half CacheLine ECC Selector

When L2C_DBG[L2T]=1/L2D_ERR[ECC_ENA]=0, the BMHCLSEL selects
                                                          which half cacheline to conditionally latch into
                                                          the L2D_FSYN0/L2D_FSYN1 registers when an LDD command
                                                          is detected from the diagnostic PP (see L2C_DBG[PPNUM]).
                                                         - 0: OW[0-3] ECC (from first 1/2 cacheline) is selected to
                                                             be conditionally latched into the L2D_FSYN0/1 CSRs.
                                                         - 1: OW[4-7] ECC (from last 1/2 cacheline) is selected to
                                                             be conditionally latched into
                                                             the L2D_FSYN0/1 CSRs. */
	uint64_t ded_err                      : 1;  /**< L2D Double Error detected (DED) */
	uint64_t sec_err                      : 1;  /**< L2D Single Error corrected (SEC) */
	uint64_t ded_intena                   : 1;  /**< L2 Data ECC Double Error Detect(DED) Interrupt Enable bit
                                                         When set, allows interrupts to be reported on double bit
                                                         (uncorrectable) errors from the L2 Data Arrays. */
	uint64_t sec_intena                   : 1;  /**< L2 Data ECC Single Error Correct(SEC) Interrupt Enable bit
                                                         When set, allows interrupts to be reported on single bit
                                                         (correctable) errors from the L2 Data Arrays. */
	uint64_t ecc_ena                      : 1;  /**< L2 Data ECC Enable
                                                         When set, enables 10-bit SEC/DED codeword for 128bit L2
                                                         Data Arrays. */
#else
	uint64_t ecc_ena                      : 1;
	uint64_t sec_intena                   : 1;
	uint64_t ded_intena                   : 1;
	uint64_t sec_err                      : 1;
	uint64_t ded_err                      : 1;
	uint64_t bmhclsel                     : 1;
	uint64_t reserved_6_63                : 58;
#endif
	} s;
	struct cvmx_l2d_err_s                 cn30xx;
	struct cvmx_l2d_err_s                 cn31xx;
	struct cvmx_l2d_err_s                 cn38xx;
	struct cvmx_l2d_err_s                 cn38xxp2;
	struct cvmx_l2d_err_s                 cn50xx;
	struct cvmx_l2d_err_s                 cn52xx;
	struct cvmx_l2d_err_s                 cn52xxp1;
	struct cvmx_l2d_err_s                 cn56xx;
	struct cvmx_l2d_err_s                 cn56xxp1;
	struct cvmx_l2d_err_s                 cn58xx;
	struct cvmx_l2d_err_s                 cn58xxp1;
};
typedef union cvmx_l2d_err cvmx_l2d_err_t;

/**
 * cvmx_l2d_fadr
 *
 * L2D_FADR = L2 Failing Address
 *
 * Description: L2 Data ECC SEC/DED Failing Address
 *
 * Notes:
 * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data store index.
 * (A DED Error will always overwrite a SEC Error SYNDROME and FADR).
 */
union cvmx_l2d_fadr {
	uint64_t u64;
	struct cvmx_l2d_fadr_s {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_19_63               : 45;
	uint64_t fadru                        : 1;  /**< Failing L2 Data Store Upper Index bit(MSB) */
	uint64_t fowmsk                       : 4;  /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
                                                         error) */
	uint64_t fset                         : 3;  /**< Failing SET# */
	uint64_t fadr                         : 11; /**< Failing L2 Data Store Lower Index bits
                                                         (NOTE: L2 Data Store Index is for each 1/2 cacheline)
                                                            [FADRU, FADR[10:1]]: cacheline index[17:7]
                                                            FADR[0]: 1/2 cacheline index
                                                         NOTE: FADR[1] is used to select between upper/lower 1MB
                                                         physical L2 Data Store banks. */
#else
	uint64_t fadr                         : 11;
	uint64_t fset                         : 3;
	uint64_t fowmsk                       : 4;
	uint64_t fadru                        : 1;
	uint64_t reserved_19_63               : 45;
#endif
	} s;
	struct cvmx_l2d_fadr_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_18_63               : 46;
	uint64_t fowmsk                       : 4;  /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
                                                         error) */
	uint64_t reserved_13_13               : 1;
	uint64_t fset                         : 2;  /**< Failing SET# */
	uint64_t reserved_9_10                : 2;
	uint64_t fadr                         : 9;  /**< Failing L2 Data Store Index(1of512 = 1/2 CL address) */
#else
	uint64_t fadr                         : 9;
	uint64_t reserved_9_10                : 2;
	uint64_t fset                         : 2;
	uint64_t reserved_13_13               : 1;
	uint64_t fowmsk                       : 4;
	uint64_t reserved_18_63               : 46;
#endif
	} cn30xx;
	struct cvmx_l2d_fadr_cn31xx {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_18_63               : 46;
	uint64_t fowmsk                       : 4;  /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
                                                         error) */
	uint64_t reserved_13_13               : 1;
	uint64_t fset                         : 2;  /**< Failing SET# */
	uint64_t reserved_10_10               : 1;
	uint64_t fadr                         : 10; /**< Failing L2 Data Store Index
                                                         (1 of 1024 = half cacheline indices) */
#else
	uint64_t fadr                         : 10;
	uint64_t reserved_10_10               : 1;
	uint64_t fset                         : 2;
	uint64_t reserved_13_13               : 1;
	uint64_t fowmsk                       : 4;
	uint64_t reserved_18_63               : 46;
#endif
	} cn31xx;
	struct cvmx_l2d_fadr_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_18_63               : 46;
	uint64_t fowmsk                       : 4;  /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
                                                         error) */
	uint64_t fset                         : 3;  /**< Failing SET# */
	uint64_t fadr                         : 11; /**< Failing L2 Data Store Index (1of2K = 1/2 CL address) */
#else
	uint64_t fadr                         : 11;
	uint64_t fset                         : 3;
	uint64_t fowmsk                       : 4;
	uint64_t reserved_18_63               : 46;
#endif
	} cn38xx;
	struct cvmx_l2d_fadr_cn38xx           cn38xxp2;
	struct cvmx_l2d_fadr_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_18_63               : 46;
	uint64_t fowmsk                       : 4;  /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
                                                         error) */
	uint64_t fset                         : 3;  /**< Failing SET# */
	uint64_t reserved_8_10                : 3;
	uint64_t fadr                         : 8;  /**< Failing L2 Data Store Lower Index bits
                                                         (NOTE: L2 Data Store Index is for each 1/2 cacheline)
                                                            FADR[7:1]: cacheline index[13:7]
                                                            FADR[0]: 1/2 cacheline index */
#else
	uint64_t fadr                         : 8;
	uint64_t reserved_8_10                : 3;
	uint64_t fset                         : 3;
	uint64_t fowmsk                       : 4;
	uint64_t reserved_18_63               : 46;
#endif
	} cn50xx;
	struct cvmx_l2d_fadr_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_18_63               : 46;
	uint64_t fowmsk                       : 4;  /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
                                                         error) */
	uint64_t fset                         : 3;  /**< Failing SET# */
	uint64_t reserved_10_10               : 1;
	uint64_t fadr                         : 10; /**< Failing L2 Data Store Lower Index bits
                                                         (NOTE: L2 Data Store Index is for each 1/2 cacheline)
                                                            FADR[9:1]: cacheline index[15:7]
                                                            FADR[0]: 1/2 cacheline index */
#else
	uint64_t fadr                         : 10;
	uint64_t reserved_10_10               : 1;
	uint64_t fset                         : 3;
	uint64_t fowmsk                       : 4;
	uint64_t reserved_18_63               : 46;
#endif
	} cn52xx;
	struct cvmx_l2d_fadr_cn52xx           cn52xxp1;
	struct cvmx_l2d_fadr_s                cn56xx;
	struct cvmx_l2d_fadr_s                cn56xxp1;
	struct cvmx_l2d_fadr_s                cn58xx;
	struct cvmx_l2d_fadr_s                cn58xxp1;
};
typedef union cvmx_l2d_fadr cvmx_l2d_fadr_t;

/**
 * cvmx_l2d_fsyn0
 *
 * L2D_FSYN0 = L2 Failing Syndrome [OW0,4 / OW1,5]
 *
 * Description: L2 Data ECC SEC/DED Failing Syndrome for lower cache line
 *
 * Notes:
 * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data ECC 10b syndrome.
 * (A DED Error will always overwrite a SEC Error SYNDROME and FADR).
 */
union cvmx_l2d_fsyn0 {
	uint64_t u64;
	struct cvmx_l2d_fsyn0_s {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_20_63               : 44;
	uint64_t fsyn_ow1                     : 10; /**< Failing L2 Data Store SYNDROME OW[1,5]
                                                         When L2D_ERR[ECC_ENA]=1 and either L2D_ERR[SEC_ERR]
                                                         or L2D_ERR[DED_ERR] are set, this field represents
                                                         the failing OWECC syndrome for the half cacheline
                                                         indexed by L2D_FADR[FADR].
                                                         NOTE: The L2D_FADR[FOWMSK] further qualifies which
                                                         OW lane(1of4) detected the error.
                                                         When L2C_DBG[L2T]=1 and L2D_ERR[ECC_ENA]=0, an LDD
                                                         command from the diagnostic PP will conditionally latch
                                                         the raw OWECC for the selected half cacheline.
                                                         (see: L2D_ERR[BMHCLSEL] */
	uint64_t fsyn_ow0                     : 10; /**< Failing L2 Data Store SYNDROME OW[0,4]
                                                         When L2D_ERR[ECC_ENA]=1 and either L2D_ERR[SEC_ERR]
                                                         or L2D_ERR[DED_ERR] are set, this field represents
                                                         the failing OWECC syndrome for the half cacheline
                                                         indexed by L2D_FADR[FADR].
                                                         NOTE: The L2D_FADR[FOWMSK] further qualifies which
                                                         OW lane(1of4) detected the error.
                                                         When L2C_DBG[L2T]=1 and L2D_ERR[ECC_ENA]=0, an LDD
                                                         (L1 load-miss) from the diagnostic PP will conditionally
                                                         latch the raw OWECC for the selected half cacheline.
                                                         (see: L2D_ERR[BMHCLSEL] */
#else
	uint64_t fsyn_ow0                     : 10;
	uint64_t fsyn_ow1                     : 10;
	uint64_t reserved_20_63               : 44;
#endif
	} s;
	struct cvmx_l2d_fsyn0_s               cn30xx;
	struct cvmx_l2d_fsyn0_s               cn31xx;
	struct cvmx_l2d_fsyn0_s               cn38xx;
	struct cvmx_l2d_fsyn0_s               cn38xxp2;
	struct cvmx_l2d_fsyn0_s               cn50xx;
	struct cvmx_l2d_fsyn0_s               cn52xx;
	struct cvmx_l2d_fsyn0_s               cn52xxp1;
	struct cvmx_l2d_fsyn0_s               cn56xx;
	struct cvmx_l2d_fsyn0_s               cn56xxp1;
	struct cvmx_l2d_fsyn0_s               cn58xx;
	struct cvmx_l2d_fsyn0_s               cn58xxp1;
};
typedef union cvmx_l2d_fsyn0 cvmx_l2d_fsyn0_t;

/**
 * cvmx_l2d_fsyn1
 *
 * L2D_FSYN1 = L2 Failing Syndrome [OW2,6 / OW3,7]
 *
 * Description: L2 Data ECC SEC/DED Failing Syndrome for upper cache line
 *
 * Notes:
 * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data ECC 10b syndrome.
 * (A DED Error will always overwrite a SEC Error SYNDROME and FADR).
 */
union cvmx_l2d_fsyn1 {
	uint64_t u64;
	struct cvmx_l2d_fsyn1_s {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_20_63               : 44;
	uint64_t fsyn_ow3                     : 10; /**< Failing L2 Data Store SYNDROME OW[3,7] */
	uint64_t fsyn_ow2                     : 10; /**< Failing L2 Data Store SYNDROME OW[2,5] */
#else
	uint64_t fsyn_ow2                     : 10;
	uint64_t fsyn_ow3                     : 10;
	uint64_t reserved_20_63               : 44;
#endif
	} s;
	struct cvmx_l2d_fsyn1_s               cn30xx;
	struct cvmx_l2d_fsyn1_s               cn31xx;
	struct cvmx_l2d_fsyn1_s               cn38xx;
	struct cvmx_l2d_fsyn1_s               cn38xxp2;
	struct cvmx_l2d_fsyn1_s               cn50xx;
	struct cvmx_l2d_fsyn1_s               cn52xx;
	struct cvmx_l2d_fsyn1_s               cn52xxp1;
	struct cvmx_l2d_fsyn1_s               cn56xx;
	struct cvmx_l2d_fsyn1_s               cn56xxp1;
	struct cvmx_l2d_fsyn1_s               cn58xx;
	struct cvmx_l2d_fsyn1_s               cn58xxp1;
};
typedef union cvmx_l2d_fsyn1 cvmx_l2d_fsyn1_t;

/**
 * cvmx_l2d_fus0
 *
 * L2D_FUS0 = L2C Data Store QUAD0 Fuse Register
 *
 */
union cvmx_l2d_fus0 {
	uint64_t u64;
	struct cvmx_l2d_fus0_s {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_34_63               : 30;
	uint64_t q0fus                        : 34; /**< Fuse Register for QUAD0
                                                         This is purely for debug and not needed in the general
                                                         manufacturing flow.
                                                         Note that the fuse are complementary (Assigning a
                                                         fuse to 1 will read as a zero). This means the case
                                                         where no fuses are blown result in these csr's showing
                                                         all ones.
                                                          Failure \#1 Fuse Mapping
                                                             [16:14] bad bank
                                                             [13:7] bad high column
                                                             [6:0] bad low column
                                                           Failure \#2 Fuse Mapping
                                                             [33:31] bad bank
                                                             [30:24] bad high column
                                                             [23:17] bad low column */
#else
	uint64_t q0fus                        : 34;
	uint64_t reserved_34_63               : 30;
#endif
	} s;
	struct cvmx_l2d_fus0_s                cn30xx;
	struct cvmx_l2d_fus0_s                cn31xx;
	struct cvmx_l2d_fus0_s                cn38xx;
	struct cvmx_l2d_fus0_s                cn38xxp2;
	struct cvmx_l2d_fus0_s                cn50xx;
	struct cvmx_l2d_fus0_s                cn52xx;
	struct cvmx_l2d_fus0_s                cn52xxp1;
	struct cvmx_l2d_fus0_s                cn56xx;
	struct cvmx_l2d_fus0_s                cn56xxp1;
	struct cvmx_l2d_fus0_s                cn58xx;
	struct cvmx_l2d_fus0_s                cn58xxp1;
};
typedef union cvmx_l2d_fus0 cvmx_l2d_fus0_t;

/**
 * cvmx_l2d_fus1
 *
 * L2D_FUS1 = L2C Data Store QUAD1 Fuse Register
 *
 */
union cvmx_l2d_fus1 {
	uint64_t u64;
	struct cvmx_l2d_fus1_s {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_34_63               : 30;
	uint64_t q1fus                        : 34; /**< Fuse Register for QUAD1
                                                         This is purely for debug and not needed in the general
                                                         manufacturing flow.
                                                         Note that the fuse are complementary (Assigning a
                                                         fuse to 1 will read as a zero). This means the case
                                                         where no fuses are blown result in these csr's showing
                                                         all ones.
                                                          Failure \#1 Fuse Mapping
                                                             [16:14] bad bank
                                                             [13:7] bad high column
                                                             [6:0] bad low column
                                                           Failure \#2 Fuse Mapping
                                                             [33:31] bad bank
                                                             [30:24] bad high column
                                                             [23:17] bad low column */
#else
	uint64_t q1fus                        : 34;
	uint64_t reserved_34_63               : 30;
#endif
	} s;
	struct cvmx_l2d_fus1_s                cn30xx;
	struct cvmx_l2d_fus1_s                cn31xx;
	struct cvmx_l2d_fus1_s                cn38xx;
	struct cvmx_l2d_fus1_s                cn38xxp2;
	struct cvmx_l2d_fus1_s                cn50xx;
	struct cvmx_l2d_fus1_s                cn52xx;
	struct cvmx_l2d_fus1_s                cn52xxp1;
	struct cvmx_l2d_fus1_s                cn56xx;
	struct cvmx_l2d_fus1_s                cn56xxp1;
	struct cvmx_l2d_fus1_s                cn58xx;
	struct cvmx_l2d_fus1_s                cn58xxp1;
};
typedef union cvmx_l2d_fus1 cvmx_l2d_fus1_t;

/**
 * cvmx_l2d_fus2
 *
 * L2D_FUS2 = L2C Data Store QUAD2 Fuse Register
 *
 */
union cvmx_l2d_fus2 {
	uint64_t u64;
	struct cvmx_l2d_fus2_s {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_34_63               : 30;
	uint64_t q2fus                        : 34; /**< Fuse Register for QUAD2
                                                         This is purely for debug and not needed in the general
                                                         manufacturing flow.
                                                         Note that the fuse are complementary (Assigning a
                                                         fuse to 1 will read as a zero). This means the case
                                                         where no fuses are blown result in these csr's showing
                                                         all ones.
                                                          Failure \#1 Fuse Mapping
                                                             [16:14] bad bank
                                                             [13:7] bad high column
                                                             [6:0] bad low column
                                                           Failure \#2 Fuse Mapping
                                                             [33:31] bad bank
                                                             [30:24] bad high column
                                                             [23:17] bad low column */
#else
	uint64_t q2fus                        : 34;
	uint64_t reserved_34_63               : 30;
#endif
	} s;
	struct cvmx_l2d_fus2_s                cn30xx;
	struct cvmx_l2d_fus2_s                cn31xx;
	struct cvmx_l2d_fus2_s                cn38xx;
	struct cvmx_l2d_fus2_s                cn38xxp2;
	struct cvmx_l2d_fus2_s                cn50xx;
	struct cvmx_l2d_fus2_s                cn52xx;
	struct cvmx_l2d_fus2_s                cn52xxp1;
	struct cvmx_l2d_fus2_s                cn56xx;
	struct cvmx_l2d_fus2_s                cn56xxp1;
	struct cvmx_l2d_fus2_s                cn58xx;
	struct cvmx_l2d_fus2_s                cn58xxp1;
};
typedef union cvmx_l2d_fus2 cvmx_l2d_fus2_t;

/**
 * cvmx_l2d_fus3
 *
 * L2D_FUS3 = L2C Data Store QUAD3 Fuse Register
 *
 */
union cvmx_l2d_fus3 {
	uint64_t u64;
	struct cvmx_l2d_fus3_s {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_40_63               : 24;
	uint64_t ema_ctl                      : 3;  /**< L2 Data Store EMA Control
                                                         These bits are used to 'observe' the EMA[1:0] inputs
                                                         for the L2 Data Store RAMs which are controlled by
                                                         either FUSES[141:140] or by MIO_FUSE_EMA[EMA] CSR.
                                                         From poweron (dc_ok), the EMA_CTL are driven from
                                                         FUSE[141:140]. However after the 1st CSR write to the
                                                         MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
                                                         from the MIO_FUSE_EMA[EMA] register permanently
                                                         (until dc_ok). */
	uint64_t reserved_34_36               : 3;
	uint64_t q3fus                        : 34; /**< Fuse Register for QUAD3
                                                         This is purely for debug and not needed in the general
                                                         manufacturing flow.
                                                         Note that the fuses are complementary (Assigning a
                                                         fuse to 1 will read as a zero). This means the case
                                                         where no fuses are blown result in these csr's showing
                                                         all ones.
                                                          Failure \#1 Fuse Mapping
                                                             [16:14] bad bank
                                                             [13:7] bad high column
                                                             [6:0] bad low column
                                                           Failure \#2 Fuse Mapping
                                                             [33:31] bad bank
                                                             [30:24] bad high column
                                                             [23:17] bad low column */
#else
	uint64_t q3fus                        : 34;
	uint64_t reserved_34_36               : 3;
	uint64_t ema_ctl                      : 3;
	uint64_t reserved_40_63               : 24;
#endif
	} s;
	struct cvmx_l2d_fus3_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_35_63               : 29;
	uint64_t crip_64k                     : 1;  /**< This is purely for debug and not needed in the general
                                                         manufacturing flow.
                                                         If the FUSE is not-blown, then this bit should read
                                                         as 0. If the FUSE is blown, then this bit should read
                                                         as 1. */
	uint64_t q3fus                        : 34; /**< Fuse Register for QUAD3
                                                         This is purely for debug and not needed in the general
                                                         manufacturing flow.
                                                         Note that the fuses are complementary (Assigning a
                                                         fuse to 1 will read as a zero). This means the case
                                                         where no fuses are blown result in these csr's showing
                                                         all ones.
                                                          Failure \#1 Fuse Mapping
                                                             [16:15] UNUSED
                                                             [14]    bad bank
                                                             [13:7] bad high column
                                                             [6:0] bad low column
                                                           Failure \#2 Fuse Mapping
                                                             [33:32] UNUSED
                                                             [31]    bad bank
                                                             [30:24] bad high column
                                                             [23:17] bad low column */
#else
	uint64_t q3fus                        : 34;
	uint64_t crip_64k                     : 1;
	uint64_t reserved_35_63               : 29;
#endif
	} cn30xx;
	struct cvmx_l2d_fus3_cn31xx {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_35_63               : 29;
	uint64_t crip_128k                    : 1;  /**< This is purely for debug and not needed in the general
                                                         manufacturing flow.
                                                         If the FUSE is not-blown, then this bit should read
                                                         as 0. If the FUSE is blown, then this bit should read
                                                         as 1. */
	uint64_t q3fus                        : 34; /**< Fuse Register for QUAD3
                                                         This is purely for debug and not needed in the general
                                                         manufacturing flow.
                                                         Note that the fuses are complementary (Assigning a
                                                         fuse to 1 will read as a zero). This means the case
                                                         where no fuses are blown result in these csr's showing
                                                         all ones.
                                                          Failure \#1 Fuse Mapping
                                                             [16:15] UNUSED
                                                             [14]    bad bank
                                                             [13:7] bad high column
                                                             [6:0] bad low column
                                                           Failure \#2 Fuse Mapping
                                                             [33:32] UNUSED
                                                             [31]    bad bank
                                                             [30:24] bad high column
                                                             [23:17] bad low column */
#else
	uint64_t q3fus                        : 34;
	uint64_t crip_128k                    : 1;
	uint64_t reserved_35_63               : 29;
#endif
	} cn31xx;
	struct cvmx_l2d_fus3_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_36_63               : 28;
	uint64_t crip_256k                    : 1;  /**< This is purely for debug and not needed in the general
                                                         manufacturing flow.
                                                         If the FUSE is not-blown, then this bit should read
                                                         as 0. If the FUSE is blown, then this bit should read
                                                         as 1.
                                                         *** NOTE: Pass2 Addition */
	uint64_t crip_512k                    : 1;  /**< This is purely for debug and not needed in the general
                                                         manufacturing flow.
                                                         If the FUSE is not-blown, then this bit should read
                                                         as 0. If the FUSE is blown, then this bit should read
                                                         as 1.
                                                         *** NOTE: Pass2 Addition */
	uint64_t q3fus                        : 34; /**< Fuse Register for QUAD3
                                                         This is purely for debug and not needed in the general
                                                         manufacturing flow.
                                                         Note that the fuses are complementary (Assigning a
                                                         fuse to 1 will read as a zero). This means the case
                                                         where no fuses are blown result in these csr's showing
                                                         all ones.
                                                          Failure \#1 Fuse Mapping
                                                             [16:14] bad bank
                                                             [13:7] bad high column
                                                             [6:0] bad low column
                                                           Failure \#2 Fuse Mapping
                                                             [33:31] bad bank
                                                             [30:24] bad high column
                                                             [23:17] bad low column */
#else
	uint64_t q3fus                        : 34;
	uint64_t crip_512k                    : 1;
	uint64_t crip_256k                    : 1;
	uint64_t reserved_36_63               : 28;
#endif
	} cn38xx;
	struct cvmx_l2d_fus3_cn38xx           cn38xxp2;
	struct cvmx_l2d_fus3_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_40_63               : 24;
	uint64_t ema_ctl                      : 3;  /**< L2 Data Store EMA Control
                                                         These bits are used to 'observe' the EMA[2:0] inputs
                                                         for the L2 Data Store RAMs which are controlled by
                                                         either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR.
                                                         From poweron (dc_ok), the EMA_CTL are driven from
                                                         FUSE[141:140]. However after the 1st CSR write to the
                                                         MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
                                                         from the MIO_FUSE_EMA[EMA] register permanently
                                                         (until dc_ok). */
	uint64_t reserved_36_36               : 1;
	uint64_t crip_32k                     : 1;  /**< This is purely for debug and not needed in the general
                                                         manufacturing flow.
                                                         If the FUSE is not-blown, then this bit should read
                                                         as 0. If the FUSE is blown, then this bit should read
                                                         as 1. */
	uint64_t crip_64k                     : 1;  /**< This is purely for debug and not needed in the general
                                                         manufacturing flow.
                                                         If the FUSE is not-blown, then this bit should read
                                                         as 0. If the FUSE is blown, then this bit should read
                                                         as 1. */
	uint64_t q3fus                        : 34; /**< Fuse Register for QUAD3
                                                         This is purely for debug and not needed in the general
                                                         manufacturing flow.
                                                         Note that the fuses are complementary (Assigning a
                                                         fuse to 1 will read as a zero). This means the case
                                                         where no fuses are blown result in these csr's showing
                                                         all ones.
                                                          Failure \#1 Fuse Mapping
                                                             [16:14] UNUSED (5020 uses single physical bank per quad)
                                                             [13:7] bad high column
                                                             [6:0] bad low column
                                                           Failure \#2 Fuse Mapping
                                                             [33:31] UNUSED (5020 uses single physical bank per quad)
                                                             [30:24] bad high column
                                                             [23:17] bad low column */
#else
	uint64_t q3fus                        : 34;
	uint64_t crip_64k                     : 1;
	uint64_t crip_32k                     : 1;
	uint64_t reserved_36_36               : 1;
	uint64_t ema_ctl                      : 3;
	uint64_t reserved_40_63               : 24;
#endif
	} cn50xx;
	struct cvmx_l2d_fus3_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_40_63               : 24;
	uint64_t ema_ctl                      : 3;  /**< L2 Data Store EMA Control
                                                         These bits are used to 'observe' the EMA[2:0] inputs
                                                         for the L2 Data Store RAMs which are controlled by
                                                         either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR.
                                                         From poweron (dc_ok), the EMA_CTL are driven from
                                                         FUSE[141:140]. However after the 1st CSR write to the
                                                         MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
                                                         from the MIO_FUSE_EMA[EMA] register permanently
                                                         (until dc_ok). */
	uint64_t reserved_36_36               : 1;
	uint64_t crip_128k                    : 1;  /**< This is purely for debug and not needed in the general
                                                         manufacturing flow.
                                                         If the FUSE is not-blown, then this bit should read
                                                         as 0. If the FUSE is blown, then this bit should read
                                                         as 1. */
	uint64_t crip_256k                    : 1;  /**< This is purely for debug and not needed in the general
                                                         manufacturing flow.
                                                         If the FUSE is not-blown, then this bit should read
                                                         as 0. If the FUSE is blown, then this bit should read
                                                         as 1. */
	uint64_t q3fus                        : 34; /**< Fuse Register for QUAD3
                                                         This is purely for debug and not needed in the general
                                                         manufacturing flow.
                                                         Note that the fuses are complementary (Assigning a
                                                         fuse to 1 will read as a zero). This means the case
                                                         where no fuses are blown result in these csr's showing
                                                         all ones.
                                                          Failure \#1 Fuse Mapping
                                                             [16:14] UNUSED (5020 uses single physical bank per quad)
                                                             [13:7] bad high column
                                                             [6:0] bad low column
                                                           Failure \#2 Fuse Mapping
                                                             [33:31] UNUSED (5020 uses single physical bank per quad)
                                                             [30:24] bad high column
                                                             [23:17] bad low column */
#else
	uint64_t q3fus                        : 34;
	uint64_t crip_256k                    : 1;
	uint64_t crip_128k                    : 1;
	uint64_t reserved_36_36               : 1;
	uint64_t ema_ctl                      : 3;
	uint64_t reserved_40_63               : 24;
#endif
	} cn52xx;
	struct cvmx_l2d_fus3_cn52xx           cn52xxp1;
	struct cvmx_l2d_fus3_cn56xx {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_40_63               : 24;
	uint64_t ema_ctl                      : 3;  /**< L2 Data Store EMA Control
                                                         These bits are used to 'observe' the EMA[2:0] inputs
                                                         for the L2 Data Store RAMs which are controlled by
                                                         either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR.
                                                         From poweron (dc_ok), the EMA_CTL are driven from
                                                         FUSE[141:140]. However after the 1st CSR write to the
                                                         MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
                                                         from the MIO_FUSE_EMA[EMA] register permanently
                                                         (until dc_ok). */
	uint64_t reserved_36_36               : 1;
	uint64_t crip_512k                    : 1;  /**< This is purely for debug and not needed in the general
                                                         manufacturing flow.
                                                         If the FUSE is not-blown, then this bit should read
                                                         as 0. If the FUSE is blown, then this bit should read
                                                         as 1.
                                                         *** NOTE: Pass2 Addition */
	uint64_t crip_1024k                   : 1;  /**< This is purely for debug and not needed in the general
                                                         manufacturing flow.
                                                         If the FUSE is not-blown, then this bit should read
                                                         as 0. If the FUSE is blown, then this bit should read
                                                         as 1.
                                                         *** NOTE: Pass2 Addition */
	uint64_t q3fus                        : 34; /**< Fuse Register for QUAD3
                                                         This is purely for debug and not needed in the general
                                                         manufacturing flow.
                                                         Note that the fuses are complementary (Assigning a
                                                         fuse to 1 will read as a zero). This means the case
                                                         where no fuses are blown result in these csr's showing
                                                         all ones.
                                                          Failure \#1 Fuse Mapping
                                                             [16:14] bad bank
                                                             [13:7] bad high column
                                                             [6:0] bad low column
                                                           Failure \#2 Fuse Mapping
                                                             [33:31] bad bank
                                                             [30:24] bad high column
                                                             [23:17] bad low column */
#else
	uint64_t q3fus                        : 34;
	uint64_t crip_1024k                   : 1;
	uint64_t crip_512k                    : 1;
	uint64_t reserved_36_36               : 1;
	uint64_t ema_ctl                      : 3;
	uint64_t reserved_40_63               : 24;
#endif
	} cn56xx;
	struct cvmx_l2d_fus3_cn56xx           cn56xxp1;
	struct cvmx_l2d_fus3_cn58xx {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_39_63               : 25;
	uint64_t ema_ctl                      : 2;  /**< L2 Data Store EMA Control
                                                         These bits are used to 'observe' the EMA[1:0] inputs
                                                         for the L2 Data Store RAMs which are controlled by
                                                         either FUSES[141:140] or by MIO_FUSE_EMA[EMA] CSR.
                                                         From poweron (dc_ok), the EMA_CTL are driven from
                                                         FUSE[141:140]. However after the 1st CSR write to the
                                                         MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
                                                         from the MIO_FUSE_EMA[EMA] register permanently
                                                         (until dc_ok). */
	uint64_t reserved_36_36               : 1;
	uint64_t crip_512k                    : 1;  /**< This is purely for debug and not needed in the general
                                                         manufacturing flow.
                                                         If the FUSE is not-blown, then this bit should read
                                                         as 0. If the FUSE is blown, then this bit should read
                                                         as 1.
                                                         *** NOTE: Pass2 Addition */
	uint64_t crip_1024k                   : 1;  /**< This is purely for debug and not needed in the general
                                                         manufacturing flow.
                                                         If the FUSE is not-blown, then this bit should read
                                                         as 0. If the FUSE is blown, then this bit should read
                                                         as 1.
                                                         *** NOTE: Pass2 Addition */
	uint64_t q3fus                        : 34; /**< Fuse Register for QUAD3
                                                         This is purely for debug and not needed in the general
                                                         manufacturing flow.
                                                         Note that the fuses are complementary (Assigning a
                                                         fuse to 1 will read as a zero). This means the case
                                                         where no fuses are blown result in these csr's showing
                                                         all ones.
                                                          Failure \#1 Fuse Mapping
                                                             [16:14] bad bank
                                                             [13:7] bad high column
                                                             [6:0] bad low column
                                                           Failure \#2 Fuse Mapping
                                                             [33:31] bad bank
                                                             [30:24] bad high column
                                                             [23:17] bad low column */
#else
	uint64_t q3fus                        : 34;
	uint64_t crip_1024k                   : 1;
	uint64_t crip_512k                    : 1;
	uint64_t reserved_36_36               : 1;
	uint64_t ema_ctl                      : 2;
	uint64_t reserved_39_63               : 25;
#endif
	} cn58xx;
	struct cvmx_l2d_fus3_cn58xx           cn58xxp1;
};
typedef union cvmx_l2d_fus3 cvmx_l2d_fus3_t;

#endif

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