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📁 ..
📄 cvmip.h(5.88 KB)
📄 cvmx-abi.h(3.67 KB)
📄 cvmx-access-native.h(26.79 KB)
📄 cvmx-access.h(7.82 KB)
📄 cvmx-address.h(10.26 KB)
📄 cvmx-agl-defs.h(213.66 KB)
📄 cvmx-app-hotplug.c(27.64 KB)
📄 cvmx-app-hotplug.h(5.77 KB)
📄 cvmx-app-init-linux.c(14.29 KB)
📄 cvmx-app-init.c(22.54 KB)
📄 cvmx-app-init.h(19.32 KB)
📄 cvmx-asm.h(39.3 KB)
📄 cvmx-asx0-defs.h(5.19 KB)
📄 cvmx-asxx-defs.h(50.57 KB)
📄 cvmx-atomic.h(21.71 KB)
📄 cvmx-bootloader.h(5.64 KB)
📄 cvmx-bootmem.c(40.91 KB)
📄 cvmx-bootmem.h(18.88 KB)
📄 cvmx-ciu-defs.h(702.5 KB)
📄 cvmx-ciu2-defs.h(487.31 KB)
📄 cvmx-clock.c(4.48 KB)
📄 cvmx-clock.h(4.43 KB)
📄 cvmx-cmd-queue.c(11.84 KB)
📄 cvmx-cmd-queue.h(22 KB)
📄 cvmx-cn3010-evb-hs5.c(6.05 KB)
📄 cvmx-cn3010-evb-hs5.h(2.3 KB)
📄 cvmx-compactflash.c(12.8 KB)
📄 cvmx-compactflash.h(3.05 KB)
📄 cvmx-core.c(5.3 KB)
📄 cvmx-core.h(9.46 KB)
📄 cvmx-coremask.c(4.12 KB)
📄 cvmx-coremask.h(8.11 KB)
📄 cvmx-crypto.c(2.6 KB)
📄 cvmx-crypto.h(2.54 KB)
📄 cvmx-csr-enums.h(8.45 KB)
📄 cvmx-csr-typedefs.h(3.92 KB)
📄 cvmx-csr.h(11.46 KB)
📄 cvmx-dbg-defs.h(6.28 KB)
📄 cvmx-debug-handler.S(7.44 KB)
📄 cvmx-debug-remote.c(3.24 KB)
📄 cvmx-debug-uart.c(7.88 KB)
📄 cvmx-debug.c(55.98 KB)
📄 cvmx-debug.h(22.2 KB)
📄 cvmx-dfa-defs.h(383.08 KB)
📄 cvmx-dfa.c(3.7 KB)
📄 cvmx-dfa.h(34.87 KB)
📄 cvmx-dfm-defs.h(205.93 KB)
📄 cvmx-dma-engine.c(20.25 KB)
📄 cvmx-dma-engine.h(24.06 KB)
📄 cvmx-dpi-defs.h(107.61 KB)
📄 cvmx-ebt3000.c(3.82 KB)
📄 cvmx-ebt3000.h(2.25 KB)
📄 cvmx-endor-defs.h(311.42 KB)
📄 cvmx-eoi-defs.h(26.27 KB)
📄 cvmx-fau.h(20.31 KB)
📄 cvmx-flash.c(22.46 KB)
📄 cvmx-flash.h(3.8 KB)
📄 cvmx-fpa-defs.h(157.78 KB)
📄 cvmx-fpa.c(6.63 KB)
📄 cvmx-fpa.h(10.39 KB)
📄 cvmx-gmx.h(3.07 KB)
📄 cvmx-gmxx-defs.h(505.27 KB)
📄 cvmx-gpio-defs.h(36.89 KB)
📄 cvmx-gpio.h(5.48 KB)
📄 cvmx-helper-board.c(58 KB)
📄 cvmx-helper-board.h(7.82 KB)
📄 cvmx-helper-cfg.c(18.68 KB)
📄 cvmx-helper-cfg.h(8.1 KB)
📄 cvmx-helper-check-defines.h(4.1 KB)
📄 cvmx-helper-errata.c(11.91 KB)
📄 cvmx-helper-errata.h(3.24 KB)
📄 cvmx-helper-fpa.c(8.81 KB)
📄 cvmx-helper-fpa.h(3.21 KB)
📄 cvmx-helper-ilk.c(12.74 KB)
📄 cvmx-helper-ilk.h(3.58 KB)
📄 cvmx-helper-jtag.c(7.05 KB)
📄 cvmx-helper-jtag.h(3.91 KB)
📄 cvmx-helper-loop.c(4.35 KB)
📄 cvmx-helper-loop.h(2.78 KB)
📄 cvmx-helper-npi.c(5.72 KB)
📄 cvmx-helper-npi.h(2.82 KB)
📄 cvmx-helper-rgmii.c(19.12 KB)
📄 cvmx-helper-rgmii.h(4.5 KB)
📄 cvmx-helper-sgmii.c(27.09 KB)
📄 cvmx-helper-sgmii.h(4.3 KB)
📄 cvmx-helper-spi.c(8.4 KB)
📄 cvmx-helper-spi.h(3.68 KB)
📄 cvmx-helper-srio.c(11.58 KB)
📄 cvmx-helper-srio.h(3.6 KB)
📄 cvmx-helper-util.c(25.77 KB)
📄 cvmx-helper-util.h(9.88 KB)
📄 cvmx-helper-xaui.c(16.54 KB)
📄 cvmx-helper-xaui.h(4.29 KB)
📄 cvmx-helper.c(69.71 KB)
📄 cvmx-helper.h(12.7 KB)
📄 cvmx-hfa.c(5.04 KB)
📄 cvmx-hfa.h(10.3 KB)
📄 cvmx-higig.h(23.21 KB)
📄 cvmx-ilk-defs.h(170.31 KB)
📄 cvmx-ilk.c(45.16 KB)
📄 cvmx-ilk.h(5.89 KB)
📄 cvmx-interrupt-handler.S(5.87 KB)
📄 cvmx-interrupt.c(47.42 KB)
📄 cvmx-interrupt.h(8.07 KB)
📄 cvmx-iob-defs.h(89.11 KB)
📄 cvmx-iob1-defs.h(6.8 KB)
📄 cvmx-ipd-defs.h(186.51 KB)
📄 cvmx-ipd.c(12.88 KB)
📄 cvmx-ipd.h(6.3 KB)
📄 cvmx-ixf18201.c(12.8 KB)
📄 cvmx-ixf18201.h(3.54 KB)
📄 cvmx-key-defs.h(11 KB)
📄 cvmx-key.h(3.29 KB)
📄 cvmx-l2c-defs.h(353.27 KB)
📄 cvmx-l2c.c(52.95 KB)
📄 cvmx-l2c.h(19.72 KB)
📄 cvmx-l2d-defs.h(60.71 KB)
📄 cvmx-l2t-defs.h(50.68 KB)
📄 cvmx-led-defs.h(22.68 KB)
📄 cvmx-llm.c(36.51 KB)
📄 cvmx-llm.h(11.72 KB)
📄 cvmx-lmcx-defs.h(532.21 KB)
📄 cvmx-log-arc.S(5.67 KB)
📄 cvmx-log.c(18.26 KB)
📄 cvmx-log.h(4.95 KB)
📁 cvmx-malloc
📄 cvmx-malloc.h(7.2 KB)
📄 cvmx-mdio.h(15.99 KB)
📄 cvmx-mgmt-port.c(36.2 KB)
📄 cvmx-mgmt-port.h(7.23 KB)
📄 cvmx-mio-defs.h(454.14 KB)
📄 cvmx-mixx-defs.h(94.59 KB)
📄 cvmx-mpi-defs.h(33.42 KB)
📄 cvmx-nand.c(76.64 KB)
📄 cvmx-nand.h(26.85 KB)
📄 cvmx-ndf-defs.h(25.53 KB)
📄 cvmx-npei-defs.h(378.19 KB)
📄 cvmx-npi-defs.h(252.36 KB)
📄 cvmx-npi.h(4.69 KB)
📄 cvmx-packet.h(2.94 KB)
📄 cvmx-pci-defs.h(250.53 KB)
📄 cvmx-pci.h(2.37 KB)
📄 cvmx-pcie.c(63 KB)
📄 cvmx-pcie.h(10.08 KB)
📄 cvmx-pcieepx-defs.h(304.49 KB)
📄 cvmx-pciercx-defs.h(284.89 KB)
📄 cvmx-pcm-defs.h(12.34 KB)
📄 cvmx-pcmx-defs.h(46.12 KB)
📄 cvmx-pcsx-defs.h(71.23 KB)
📄 cvmx-pcsxx-defs.h(45.79 KB)
📄 cvmx-pemx-defs.h(68.97 KB)
📄 cvmx-pescx-defs.h(49.92 KB)
📄 cvmx-pexp-defs.h(97.89 KB)
📄 cvmx-pip-defs.h(315.91 KB)
📄 cvmx-pip.h(33.65 KB)
📄 cvmx-pko-defs.h(181.41 KB)
📄 cvmx-pko.c(32 KB)
📄 cvmx-pko.h(31.29 KB)
📄 cvmx-platform.h(7.45 KB)
📄 cvmx-pow-defs.h(93.02 KB)
📄 cvmx-pow.c(32.26 KB)
📄 cvmx-pow.h(100.93 KB)
📄 cvmx-power-throttle.c(7.25 KB)
📄 cvmx-power-throttle.h(3.85 KB)
📄 cvmx-profiler.c(7.81 KB)
📄 cvmx-profiler.h(3.15 KB)
📄 cvmx-qlm-tables.c(35.37 KB)
📄 cvmx-qlm.c(23.41 KB)
📄 cvmx-qlm.h(4.76 KB)
📄 cvmx-rad-defs.h(43.58 KB)
📄 cvmx-raid.c(4.71 KB)
📄 cvmx-raid.h(13.02 KB)
📄 cvmx-resources.config(7.66 KB)
📄 cvmx-rng.h(5.02 KB)
📄 cvmx-rnm-defs.h(13.03 KB)
📄 cvmx-rtc.h(4.21 KB)
📄 cvmx-rwlock.h(5.25 KB)
📄 cvmx-scratch.h(4.76 KB)
📄 cvmx-shared-linux-n32.ld(11.8 KB)
📄 cvmx-shared-linux-o32.ld(10.67 KB)
📄 cvmx-shared-linux.ld(11.77 KB)
📄 cvmx-shmem.c(18.89 KB)
📄 cvmx-shmem.h(4.11 KB)
📄 cvmx-sim-magic.h(5.59 KB)
📄 cvmx-sli-defs.h(312.94 KB)
📄 cvmx-smi-defs.h(4.09 KB)
📄 cvmx-smix-defs.h(21.71 KB)
📄 cvmx-spi.c(24.99 KB)
📄 cvmx-spi.h(10.22 KB)
📄 cvmx-spi4000.c(19.23 KB)
📄 cvmx-spinlock.h(11.73 KB)
📄 cvmx-spx0-defs.h(3.94 KB)
📄 cvmx-spxx-defs.h(62.44 KB)
📄 cvmx-srio.c(63.05 KB)
📄 cvmx-srio.h(26.68 KB)
📄 cvmx-sriomaintx-defs.h(222.52 KB)
📄 cvmx-sriox-defs.h(211.56 KB)
📄 cvmx-srxx-defs.h(14.41 KB)
📄 cvmx-sso-defs.h(87.33 KB)
📄 cvmx-stxx-defs.h(34.02 KB)
📄 cvmx-swap.h(4.11 KB)
📄 cvmx-sysinfo.c(8.78 KB)
📄 cvmx-sysinfo.h(6.45 KB)
📄 cvmx-thunder.c(9.22 KB)
📄 cvmx-thunder.h(4.54 KB)
📄 cvmx-tim-defs.h(58.36 KB)
📄 cvmx-tim.c(10.92 KB)
📄 cvmx-tim.h(12.1 KB)
📄 cvmx-tlb.c(10.12 KB)
📄 cvmx-tlb.h(5.07 KB)
📄 cvmx-tra-defs.h(4.59 KB)
📄 cvmx-tra.c(31.16 KB)
📄 cvmx-tra.h(34.28 KB)
📄 cvmx-trax-defs.h(197.09 KB)
📄 cvmx-twsi.c(16.25 KB)
📄 cvmx-twsi.h(10.22 KB)
📄 cvmx-uahcx-defs.h(181.38 KB)
📄 cvmx-uart.c(5.69 KB)
📄 cvmx-uart.h(4.58 KB)
📄 cvmx-uctlx-defs.h(50.26 KB)
📄 cvmx-usb.c(138.53 KB)
📄 cvmx-usb.h(46.67 KB)
📄 cvmx-usbcx-defs.h(259.23 KB)
📄 cvmx-usbd.c(36.09 KB)
📄 cvmx-usbd.h(9.82 KB)
📄 cvmx-usbnx-defs.h(136.12 KB)
📄 cvmx-utils.h(7.54 KB)
📄 cvmx-version.h(2.23 KB)
📄 cvmx-warn.c(2.75 KB)
📄 cvmx-warn.h(2.43 KB)
📄 cvmx-wqe.h(38.61 KB)
📄 cvmx-zip-defs.h(43.18 KB)
📄 cvmx-zip.c(7.37 KB)
📄 cvmx-zip.h(8.5 KB)
📄 cvmx-zone.c(4.7 KB)
📄 cvmx.h(3.5 KB)
📄 octeon-boot-info.h(8.08 KB)
📄 octeon-feature.c(4.71 KB)
📄 octeon-feature.h(11.94 KB)
📄 octeon-model.c(15.79 KB)
📄 octeon-model.h(16.53 KB)
📄 octeon-pci-console.c(19.73 KB)
📄 octeon-pci-console.h(5.18 KB)

Editing: cvmx-mdio.h

/***********************license start***************
 * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
 * reserved.
 *
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met:
 *
 *   * Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *
 *   * Redistributions in binary form must reproduce the above
 *     copyright notice, this list of conditions and the following
 *     disclaimer in the documentation and/or other materials provided
 *     with the distribution.

*   * Neither the name of Cavium Inc. nor the names of
 *     its contributors may be used to endorse or promote products
 *     derived from this software without specific prior written
 *     permission.

* This Software, including technical data, may be subject to U.S. export  control
 * laws, including the U.S. Export Administration Act and its  associated
 * regulations, and may be subject to export or import  regulations in other
 * countries.

* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
 ***********************license end**************************************/

/**
 * @file
 *
 * Interface to the SMI/MDIO hardware, including support for both IEEE 802.3
 * clause 22 and clause 45 operations.
 *
 * <hr>$Revision: 70030 $<hr>
 */

#ifndef __CVMX_MIO_H__
#define __CVMX_MIO_H__

#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-clock.h>
#else
#include "cvmx-clock.h"
#endif

#ifdef	__cplusplus
extern "C" {
#endif

/**
 * PHY register 0 from the 802.3 spec
 */
#define CVMX_MDIO_PHY_REG_CONTROL 0
typedef union
{
    uint16_t u16;
    struct
    {
        uint16_t reset : 1;
        uint16_t loopback : 1;
        uint16_t speed_lsb : 1;
        uint16_t autoneg_enable : 1;
        uint16_t power_down : 1;
        uint16_t isolate : 1;
        uint16_t restart_autoneg : 1;
        uint16_t duplex : 1;
        uint16_t collision_test : 1;
        uint16_t speed_msb : 1;
        uint16_t unidirectional_enable : 1;
        uint16_t reserved_0_4 : 5;
    } s;
} cvmx_mdio_phy_reg_control_t;

/**
 * PHY register 1 from the 802.3 spec
 */
#define CVMX_MDIO_PHY_REG_STATUS 1
typedef union
{
    uint16_t u16;
    struct
    {
        uint16_t capable_100base_t4 : 1;
        uint16_t capable_100base_x_full : 1;
        uint16_t capable_100base_x_half : 1;
        uint16_t capable_10_full : 1;
        uint16_t capable_10_half : 1;
        uint16_t capable_100base_t2_full : 1;
        uint16_t capable_100base_t2_half : 1;
        uint16_t capable_extended_status : 1;
        uint16_t capable_unidirectional : 1;
        uint16_t capable_mf_preamble_suppression : 1;
        uint16_t autoneg_complete : 1;
        uint16_t remote_fault : 1;
        uint16_t capable_autoneg : 1;
        uint16_t link_status : 1;
        uint16_t jabber_detect : 1;
        uint16_t capable_extended_registers : 1;

} s;
} cvmx_mdio_phy_reg_status_t;

/**
 * PHY register 2 from the 802.3 spec
 */
#define CVMX_MDIO_PHY_REG_ID1 2
typedef union
{
    uint16_t u16;
    struct
    {
        uint16_t oui_bits_3_18;
    } s;
} cvmx_mdio_phy_reg_id1_t;

/**
 * PHY register 3 from the 802.3 spec
 */
#define CVMX_MDIO_PHY_REG_ID2 3
typedef union
{
    uint16_t u16;
    struct
    {
        uint16_t oui_bits_19_24 : 6;
        uint16_t model : 6;
        uint16_t revision : 4;
    } s;
} cvmx_mdio_phy_reg_id2_t;

/**
 * PHY register 4 from the 802.3 spec
 */
#define CVMX_MDIO_PHY_REG_AUTONEG_ADVER 4
typedef union
{
    uint16_t u16;
    struct
    {
        uint16_t next_page : 1;
        uint16_t reserved_14 : 1;
        uint16_t remote_fault : 1;
        uint16_t reserved_12 : 1;
        uint16_t asymmetric_pause : 1;
        uint16_t pause : 1;
        uint16_t advert_100base_t4 : 1;
        uint16_t advert_100base_tx_full : 1;
        uint16_t advert_100base_tx_half : 1;
        uint16_t advert_10base_tx_full : 1;
        uint16_t advert_10base_tx_half : 1;
        uint16_t selector : 5;
    } s;
} cvmx_mdio_phy_reg_autoneg_adver_t;

/**
 * PHY register 5 from the 802.3 spec
 */
#define CVMX_MDIO_PHY_REG_LINK_PARTNER_ABILITY 5
typedef union
{
    uint16_t u16;
    struct
    {
        uint16_t next_page : 1;
        uint16_t ack : 1;
        uint16_t remote_fault : 1;
        uint16_t reserved_12 : 1;
        uint16_t asymmetric_pause : 1;
        uint16_t pause : 1;
        uint16_t advert_100base_t4 : 1;
        uint16_t advert_100base_tx_full : 1;
        uint16_t advert_100base_tx_half : 1;
        uint16_t advert_10base_tx_full : 1;
        uint16_t advert_10base_tx_half : 1;
        uint16_t selector : 5;
    } s;
} cvmx_mdio_phy_reg_link_partner_ability_t;

/**
 * PHY register 6 from the 802.3 spec
 */
#define CVMX_MDIO_PHY_REG_AUTONEG_EXPANSION 6
typedef union
{
    uint16_t u16;
    struct
    {
        uint16_t reserved_5_15 : 11;
        uint16_t parallel_detection_fault : 1;
        uint16_t link_partner_next_page_capable : 1;
        uint16_t local_next_page_capable : 1;
        uint16_t page_received : 1;
        uint16_t link_partner_autoneg_capable : 1;

} s;
} cvmx_mdio_phy_reg_autoneg_expansion_t;

/**
 * PHY register 9 from the 802.3 spec
 */
#define CVMX_MDIO_PHY_REG_CONTROL_1000 9
typedef union
{
    uint16_t u16;
    struct
    {
        uint16_t test_mode : 3;
        uint16_t manual_master_slave : 1;
        uint16_t master : 1;
        uint16_t port_type : 1;
        uint16_t advert_1000base_t_full : 1;
        uint16_t advert_1000base_t_half : 1;
        uint16_t reserved_0_7 : 8;
    } s;
} cvmx_mdio_phy_reg_control_1000_t;

/**
 * PHY register 10 from the 802.3 spec
 */
#define CVMX_MDIO_PHY_REG_STATUS_1000 10
typedef union
{
    uint16_t u16;
    struct
    {
        uint16_t master_slave_fault : 1;
        uint16_t is_master : 1;
        uint16_t local_receiver_ok : 1;
        uint16_t remote_receiver_ok : 1;
        uint16_t remote_capable_1000base_t_full : 1;
        uint16_t remote_capable_1000base_t_half : 1;
        uint16_t reserved_8_9 : 2;
        uint16_t idle_error_count : 8;
    } s;
} cvmx_mdio_phy_reg_status_1000_t;

/**
 * PHY register 15 from the 802.3 spec
 */
#define CVMX_MDIO_PHY_REG_EXTENDED_STATUS 15
typedef union
{
    uint16_t u16;
    struct
    {
        uint16_t capable_1000base_x_full : 1;
        uint16_t capable_1000base_x_half : 1;
        uint16_t capable_1000base_t_full : 1;
        uint16_t capable_1000base_t_half : 1;
        uint16_t reserved_0_11 : 12;
    } s;
} cvmx_mdio_phy_reg_extended_status_t;

/**
 * PHY register 13 from the 802.3 spec
 */
#define CVMX_MDIO_PHY_REG_MMD_CONTROL 13
typedef union
{
    uint16_t u16;
    struct
    {
        uint16_t function : 2;
        uint16_t reserved_5_13 : 9;
        uint16_t devad : 5;
    } s;
} cvmx_mdio_phy_reg_mmd_control_t;

/**
 * PHY register 14 from the 802.3 spec
 */
#define CVMX_MDIO_PHY_REG_MMD_ADDRESS_DATA 14
typedef union
{
    uint16_t u16;
    struct
    {
        uint16_t address_data : 16;
    } s;
} cvmx_mdio_phy_reg_mmd_address_data_t;

/* Operating request encodings. */
#define MDIO_CLAUSE_22_WRITE    0
#define MDIO_CLAUSE_22_READ     1

#define MDIO_CLAUSE_45_ADDRESS  0
#define MDIO_CLAUSE_45_WRITE    1
#define MDIO_CLAUSE_45_READ_INC 2
#define MDIO_CLAUSE_45_READ     3

/* MMD identifiers, mostly for accessing devices within XENPAK modules. */
#define CVMX_MMD_DEVICE_PMA_PMD      1
#define CVMX_MMD_DEVICE_WIS          2
#define CVMX_MMD_DEVICE_PCS          3
#define CVMX_MMD_DEVICE_PHY_XS       4
#define CVMX_MMD_DEVICE_DTS_XS       5
#define CVMX_MMD_DEVICE_TC           6
#define CVMX_MMD_DEVICE_CL22_EXT     29
#define CVMX_MMD_DEVICE_VENDOR_1     30
#define CVMX_MMD_DEVICE_VENDOR_2     31

#define CVMX_MDIO_TIMEOUT   100000 /* 100 millisec */

/* Helper function to put MDIO interface into clause 45 mode */
static inline void __cvmx_mdio_set_clause45_mode(int bus_id)
{
    cvmx_smix_clk_t smi_clk;
    /* Put bus into clause 45 mode */
    smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id));
    smi_clk.s.mode = 1;
    smi_clk.s.preamble = 1;
    cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64);
}
/* Helper function to put MDIO interface into clause 22 mode */
static inline void __cvmx_mdio_set_clause22_mode(int bus_id)
{
    cvmx_smix_clk_t smi_clk;
    /* Put bus into clause 22 mode */
    smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id));
    smi_clk.s.mode = 0;
    cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64);
}

/**
 * @INTERNAL
 * Function to read SMIX_RD_DAT and check for timeouts. This
 * code sequence is done fairly often, so put in in one spot.
 *
 * @param bus_id SMI/MDIO bus to read
 *
 * @return Value of SMIX_RD_DAT. pending will be set on
 *         a timeout.
 */
static inline cvmx_smix_rd_dat_t __cvmx_mdio_read_rd_dat(int bus_id)
{
    cvmx_smix_rd_dat_t smi_rd;
    uint64_t done = cvmx_get_cycle() + (uint64_t)CVMX_MDIO_TIMEOUT *
                       cvmx_clock_get_rate(CVMX_CLOCK_CORE) / 1000000;
    do
    {
        cvmx_wait(1000);
        smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id));
    } while (smi_rd.s.pending && (cvmx_get_cycle() < done));
    return smi_rd;
}

/**
 * Perform an MII read. This function is used to read PHY
 * registers controlling auto negotiation.
 *
 * @param bus_id   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
 *                 support multiple busses.
 * @param phy_id   The MII phy id
 * @param location Register location to read
 *
 * @return Result from the read or -1 on failure
 */
static inline int cvmx_mdio_read(int bus_id, int phy_id, int location)
{
#if defined(CVMX_BUILD_FOR_LINUX_KERNEL) && defined(CONFIG_PHYLIB)
	struct mii_bus *bus;
	int rv;

BUG_ON(bus_id > 3 || bus_id < 0);

bus = octeon_mdiobuses[bus_id];
	if (bus == NULL)
		return -1;

rv = mdiobus_read(bus, phy_id, location);

if (rv < 0)
		return -1;
	return rv;
#else
    cvmx_smix_cmd_t smi_cmd;
    cvmx_smix_rd_dat_t smi_rd;

if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
        __cvmx_mdio_set_clause22_mode(bus_id);

smi_cmd.u64 = 0;
    smi_cmd.s.phy_op = MDIO_CLAUSE_22_READ;
    smi_cmd.s.phy_adr = phy_id;
    smi_cmd.s.reg_adr = location;
    cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);

smi_rd = __cvmx_mdio_read_rd_dat(bus_id);
    if (smi_rd.s.val)
        return smi_rd.s.dat;
    else
        return -1;
#endif
}

/**
 * Perform an MII write. This function is used to write PHY
 * registers controlling auto negotiation.
 *
 * @param bus_id   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
 *                 support multiple busses.
 * @param phy_id   The MII phy id
 * @param location Register location to write
 * @param val      Value to write
 *
 * @return -1 on error
 *         0 on success
 */
static inline int cvmx_mdio_write(int bus_id, int phy_id, int location, int val)
{
#if defined(CVMX_BUILD_FOR_LINUX_KERNEL) && defined(CONFIG_PHYLIB)
	struct mii_bus *bus;
	int rv;

BUG_ON(bus_id > 3 || bus_id < 0);

bus = octeon_mdiobuses[bus_id];
	if (bus == NULL)
		return -1;

rv = mdiobus_write(bus, phy_id, location, (u16)val);

if (rv < 0)
		return -1;
	return 0;
#else
     cvmx_smix_cmd_t smi_cmd;
    cvmx_smix_wr_dat_t smi_wr;

if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
        __cvmx_mdio_set_clause22_mode(bus_id);

smi_wr.u64 = 0;
    smi_wr.s.dat = val;
    cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);

smi_cmd.u64 = 0;
    smi_cmd.s.phy_op = MDIO_CLAUSE_22_WRITE;
    smi_cmd.s.phy_adr = phy_id;
    smi_cmd.s.reg_adr = location;
    cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);

if (CVMX_WAIT_FOR_FIELD64(CVMX_SMIX_WR_DAT(bus_id),
        cvmx_smix_wr_dat_t, pending, ==, 0, CVMX_MDIO_TIMEOUT))
        return -1;

return 0;
#endif
}

#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
/**
 * Perform an IEEE 802.3 clause 45 MII read. This function is used to read PHY
 * registers controlling auto negotiation.
 *
 * @param bus_id   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
 *                 support multiple busses.
 * @param phy_id   The MII phy id
 * @param device   MDIO Managable Device (MMD) id
 * @param location Register location to read
 *
 * @return Result from the read or -1 on failure
 */

static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device, int location)
{
    cvmx_smix_cmd_t smi_cmd;
    cvmx_smix_rd_dat_t smi_rd;
    cvmx_smix_wr_dat_t smi_wr;

if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
        return -1;

__cvmx_mdio_set_clause45_mode(bus_id);

smi_wr.u64 = 0;
    smi_wr.s.dat = location;
    cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);

smi_cmd.u64 = 0;
    smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS;
    smi_cmd.s.phy_adr = phy_id;
    smi_cmd.s.reg_adr = device;
    cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);

if (CVMX_WAIT_FOR_FIELD64(CVMX_SMIX_WR_DAT(bus_id),
        cvmx_smix_wr_dat_t, pending, ==, 0, CVMX_MDIO_TIMEOUT))
    {
        cvmx_dprintf ("cvmx_mdio_45_read: bus_id %d phy_id %2d device %2d register %2d   TIME OUT(address)\n", bus_id, phy_id, device, location);
        return -1;
    }

smi_cmd.u64 = 0;
    smi_cmd.s.phy_op = MDIO_CLAUSE_45_READ;
    smi_cmd.s.phy_adr = phy_id;
    smi_cmd.s.reg_adr = device;
    cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);

smi_rd = __cvmx_mdio_read_rd_dat(bus_id);
    if (smi_rd.s.pending)
    {
        cvmx_dprintf ("cvmx_mdio_45_read: bus_id %d phy_id %2d device %2d register %2d   TIME OUT(data)\n", bus_id, phy_id, device, location);
        return -1;
    }

if (smi_rd.s.val)
        return smi_rd.s.dat;
    else
    {
        cvmx_dprintf ("cvmx_mdio_45_read: bus_id %d phy_id %2d device %2d register %2d   INVALID READ\n", bus_id, phy_id, device, location);
        return -1;
    }
}

/**
 * Perform an IEEE 802.3 clause 45 MII write. This function is used to write PHY
 * registers controlling auto negotiation.
 *
 * @param bus_id   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
 *                 support multiple busses.
 * @param phy_id   The MII phy id
 * @param device   MDIO Managable Device (MMD) id
 * @param location Register location to write
 * @param val      Value to write
 *
 * @return -1 on error
 *         0 on success
 */
static inline int cvmx_mdio_45_write(int bus_id, int phy_id, int device, int location,
                                     int val)
{
    cvmx_smix_cmd_t smi_cmd;
    cvmx_smix_wr_dat_t smi_wr;

if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
        return -1;

__cvmx_mdio_set_clause45_mode(bus_id);

smi_wr.u64 = 0;
    smi_wr.s.dat = location;
    cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);

smi_cmd.u64 = 0;
    smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS;
    smi_cmd.s.phy_adr = phy_id;
    smi_cmd.s.reg_adr = device;
    cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);

if (CVMX_WAIT_FOR_FIELD64(CVMX_SMIX_WR_DAT(bus_id),
        cvmx_smix_wr_dat_t, pending, ==, 0, CVMX_MDIO_TIMEOUT))
        return -1;

smi_wr.u64 = 0;
    smi_wr.s.dat = val;
    cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);

smi_cmd.u64 = 0;
    smi_cmd.s.phy_op = MDIO_CLAUSE_45_WRITE;
    smi_cmd.s.phy_adr = phy_id;
    smi_cmd.s.reg_adr = device;
    cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);

if (CVMX_WAIT_FOR_FIELD64(CVMX_SMIX_WR_DAT(bus_id),
        cvmx_smix_wr_dat_t, pending, ==, 0, CVMX_MDIO_TIMEOUT))
        return -1;

return 0;
}
#endif

#ifdef	__cplusplus
}
#endif

#endif

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