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📁 ..
📄 cvmip.h(5.88 KB)
📄 cvmx-abi.h(3.67 KB)
📄 cvmx-access-native.h(26.79 KB)
📄 cvmx-access.h(7.82 KB)
📄 cvmx-address.h(10.26 KB)
📄 cvmx-agl-defs.h(213.66 KB)
📄 cvmx-app-hotplug.c(27.64 KB)
📄 cvmx-app-hotplug.h(5.77 KB)
📄 cvmx-app-init-linux.c(14.29 KB)
📄 cvmx-app-init.c(22.54 KB)
📄 cvmx-app-init.h(19.32 KB)
📄 cvmx-asm.h(39.3 KB)
📄 cvmx-asx0-defs.h(5.19 KB)
📄 cvmx-asxx-defs.h(50.57 KB)
📄 cvmx-atomic.h(21.71 KB)
📄 cvmx-bootloader.h(5.64 KB)
📄 cvmx-bootmem.c(40.91 KB)
📄 cvmx-bootmem.h(18.88 KB)
📄 cvmx-ciu-defs.h(702.5 KB)
📄 cvmx-ciu2-defs.h(487.31 KB)
📄 cvmx-clock.c(4.48 KB)
📄 cvmx-clock.h(4.43 KB)
📄 cvmx-cmd-queue.c(11.84 KB)
📄 cvmx-cmd-queue.h(22 KB)
📄 cvmx-cn3010-evb-hs5.c(6.05 KB)
📄 cvmx-cn3010-evb-hs5.h(2.3 KB)
📄 cvmx-compactflash.c(12.8 KB)
📄 cvmx-compactflash.h(3.05 KB)
📄 cvmx-core.c(5.3 KB)
📄 cvmx-core.h(9.46 KB)
📄 cvmx-coremask.c(4.12 KB)
📄 cvmx-coremask.h(8.11 KB)
📄 cvmx-crypto.c(2.6 KB)
📄 cvmx-crypto.h(2.54 KB)
📄 cvmx-csr-enums.h(8.45 KB)
📄 cvmx-csr-typedefs.h(3.92 KB)
📄 cvmx-csr.h(11.46 KB)
📄 cvmx-dbg-defs.h(6.28 KB)
📄 cvmx-debug-handler.S(7.44 KB)
📄 cvmx-debug-remote.c(3.24 KB)
📄 cvmx-debug-uart.c(7.88 KB)
📄 cvmx-debug.c(55.98 KB)
📄 cvmx-debug.h(22.2 KB)
📄 cvmx-dfa-defs.h(383.08 KB)
📄 cvmx-dfa.c(3.7 KB)
📄 cvmx-dfa.h(34.87 KB)
📄 cvmx-dfm-defs.h(205.93 KB)
📄 cvmx-dma-engine.c(20.25 KB)
📄 cvmx-dma-engine.h(24.06 KB)
📄 cvmx-dpi-defs.h(107.61 KB)
📄 cvmx-ebt3000.c(3.82 KB)
📄 cvmx-ebt3000.h(2.25 KB)
📄 cvmx-endor-defs.h(311.42 KB)
📄 cvmx-eoi-defs.h(26.27 KB)
📄 cvmx-fau.h(20.31 KB)
📄 cvmx-flash.c(22.46 KB)
📄 cvmx-flash.h(3.8 KB)
📄 cvmx-fpa-defs.h(157.78 KB)
📄 cvmx-fpa.c(6.63 KB)
📄 cvmx-fpa.h(10.39 KB)
📄 cvmx-gmx.h(3.07 KB)
📄 cvmx-gmxx-defs.h(505.27 KB)
📄 cvmx-gpio-defs.h(36.89 KB)
📄 cvmx-gpio.h(5.48 KB)
📄 cvmx-helper-board.c(58 KB)
📄 cvmx-helper-board.h(7.82 KB)
📄 cvmx-helper-cfg.c(18.68 KB)
📄 cvmx-helper-cfg.h(8.1 KB)
📄 cvmx-helper-check-defines.h(4.1 KB)
📄 cvmx-helper-errata.c(11.91 KB)
📄 cvmx-helper-errata.h(3.24 KB)
📄 cvmx-helper-fpa.c(8.81 KB)
📄 cvmx-helper-fpa.h(3.21 KB)
📄 cvmx-helper-ilk.c(12.74 KB)
📄 cvmx-helper-ilk.h(3.58 KB)
📄 cvmx-helper-jtag.c(7.05 KB)
📄 cvmx-helper-jtag.h(3.91 KB)
📄 cvmx-helper-loop.c(4.35 KB)
📄 cvmx-helper-loop.h(2.78 KB)
📄 cvmx-helper-npi.c(5.72 KB)
📄 cvmx-helper-npi.h(2.82 KB)
📄 cvmx-helper-rgmii.c(19.12 KB)
📄 cvmx-helper-rgmii.h(4.5 KB)
📄 cvmx-helper-sgmii.c(27.09 KB)
📄 cvmx-helper-sgmii.h(4.3 KB)
📄 cvmx-helper-spi.c(8.4 KB)
📄 cvmx-helper-spi.h(3.68 KB)
📄 cvmx-helper-srio.c(11.58 KB)
📄 cvmx-helper-srio.h(3.6 KB)
📄 cvmx-helper-util.c(25.77 KB)
📄 cvmx-helper-util.h(9.88 KB)
📄 cvmx-helper-xaui.c(16.54 KB)
📄 cvmx-helper-xaui.h(4.29 KB)
📄 cvmx-helper.c(69.71 KB)
📄 cvmx-helper.h(12.7 KB)
📄 cvmx-hfa.c(5.04 KB)
📄 cvmx-hfa.h(10.3 KB)
📄 cvmx-higig.h(23.21 KB)
📄 cvmx-ilk-defs.h(170.31 KB)
📄 cvmx-ilk.c(45.16 KB)
📄 cvmx-ilk.h(5.89 KB)
📄 cvmx-interrupt-handler.S(5.87 KB)
📄 cvmx-interrupt.c(47.42 KB)
📄 cvmx-interrupt.h(8.07 KB)
📄 cvmx-iob-defs.h(89.11 KB)
📄 cvmx-iob1-defs.h(6.8 KB)
📄 cvmx-ipd-defs.h(186.51 KB)
📄 cvmx-ipd.c(12.88 KB)
📄 cvmx-ipd.h(6.3 KB)
📄 cvmx-ixf18201.c(12.8 KB)
📄 cvmx-ixf18201.h(3.54 KB)
📄 cvmx-key-defs.h(11 KB)
📄 cvmx-key.h(3.29 KB)
📄 cvmx-l2c-defs.h(353.27 KB)
📄 cvmx-l2c.c(52.95 KB)
📄 cvmx-l2c.h(19.72 KB)
📄 cvmx-l2d-defs.h(60.71 KB)
📄 cvmx-l2t-defs.h(50.68 KB)
📄 cvmx-led-defs.h(22.68 KB)
📄 cvmx-llm.c(36.51 KB)
📄 cvmx-llm.h(11.72 KB)
📄 cvmx-lmcx-defs.h(532.21 KB)
📄 cvmx-log-arc.S(5.67 KB)
📄 cvmx-log.c(18.26 KB)
📄 cvmx-log.h(4.95 KB)
📁 cvmx-malloc
📄 cvmx-malloc.h(7.2 KB)
📄 cvmx-mdio.h(15.99 KB)
📄 cvmx-mgmt-port.c(36.2 KB)
📄 cvmx-mgmt-port.h(7.23 KB)
📄 cvmx-mio-defs.h(454.14 KB)
📄 cvmx-mixx-defs.h(94.59 KB)
📄 cvmx-mpi-defs.h(33.42 KB)
📄 cvmx-nand.c(76.64 KB)
📄 cvmx-nand.h(26.85 KB)
📄 cvmx-ndf-defs.h(25.53 KB)
📄 cvmx-npei-defs.h(378.19 KB)
📄 cvmx-npi-defs.h(252.36 KB)
📄 cvmx-npi.h(4.69 KB)
📄 cvmx-packet.h(2.94 KB)
📄 cvmx-pci-defs.h(250.53 KB)
📄 cvmx-pci.h(2.37 KB)
📄 cvmx-pcie.c(63 KB)
📄 cvmx-pcie.h(10.08 KB)
📄 cvmx-pcieepx-defs.h(304.49 KB)
📄 cvmx-pciercx-defs.h(284.89 KB)
📄 cvmx-pcm-defs.h(12.34 KB)
📄 cvmx-pcmx-defs.h(46.12 KB)
📄 cvmx-pcsx-defs.h(71.23 KB)
📄 cvmx-pcsxx-defs.h(45.79 KB)
📄 cvmx-pemx-defs.h(68.97 KB)
📄 cvmx-pescx-defs.h(49.92 KB)
📄 cvmx-pexp-defs.h(97.89 KB)
📄 cvmx-pip-defs.h(315.91 KB)
📄 cvmx-pip.h(33.65 KB)
📄 cvmx-pko-defs.h(181.41 KB)
📄 cvmx-pko.c(32 KB)
📄 cvmx-pko.h(31.29 KB)
📄 cvmx-platform.h(7.45 KB)
📄 cvmx-pow-defs.h(93.02 KB)
📄 cvmx-pow.c(32.26 KB)
📄 cvmx-pow.h(100.93 KB)
📄 cvmx-power-throttle.c(7.25 KB)
📄 cvmx-power-throttle.h(3.85 KB)
📄 cvmx-profiler.c(7.81 KB)
📄 cvmx-profiler.h(3.15 KB)
📄 cvmx-qlm-tables.c(35.37 KB)
📄 cvmx-qlm.c(23.41 KB)
📄 cvmx-qlm.h(4.76 KB)
📄 cvmx-rad-defs.h(43.58 KB)
📄 cvmx-raid.c(4.71 KB)
📄 cvmx-raid.h(13.02 KB)
📄 cvmx-resources.config(7.66 KB)
📄 cvmx-rng.h(5.02 KB)
📄 cvmx-rnm-defs.h(13.03 KB)
📄 cvmx-rtc.h(4.21 KB)
📄 cvmx-rwlock.h(5.25 KB)
📄 cvmx-scratch.h(4.76 KB)
📄 cvmx-shared-linux-n32.ld(11.8 KB)
📄 cvmx-shared-linux-o32.ld(10.67 KB)
📄 cvmx-shared-linux.ld(11.77 KB)
📄 cvmx-shmem.c(18.89 KB)
📄 cvmx-shmem.h(4.11 KB)
📄 cvmx-sim-magic.h(5.59 KB)
📄 cvmx-sli-defs.h(312.94 KB)
📄 cvmx-smi-defs.h(4.09 KB)
📄 cvmx-smix-defs.h(21.71 KB)
📄 cvmx-spi.c(24.99 KB)
📄 cvmx-spi.h(10.22 KB)
📄 cvmx-spi4000.c(19.23 KB)
📄 cvmx-spinlock.h(11.73 KB)
📄 cvmx-spx0-defs.h(3.94 KB)
📄 cvmx-spxx-defs.h(62.44 KB)
📄 cvmx-srio.c(63.05 KB)
📄 cvmx-srio.h(26.68 KB)
📄 cvmx-sriomaintx-defs.h(222.52 KB)
📄 cvmx-sriox-defs.h(211.56 KB)
📄 cvmx-srxx-defs.h(14.41 KB)
📄 cvmx-sso-defs.h(87.33 KB)
📄 cvmx-stxx-defs.h(34.02 KB)
📄 cvmx-swap.h(4.11 KB)
📄 cvmx-sysinfo.c(8.78 KB)
📄 cvmx-sysinfo.h(6.45 KB)
📄 cvmx-thunder.c(9.22 KB)
📄 cvmx-thunder.h(4.54 KB)
📄 cvmx-tim-defs.h(58.36 KB)
📄 cvmx-tim.c(10.92 KB)
📄 cvmx-tim.h(12.1 KB)
📄 cvmx-tlb.c(10.12 KB)
📄 cvmx-tlb.h(5.07 KB)
📄 cvmx-tra-defs.h(4.59 KB)
📄 cvmx-tra.c(31.16 KB)
📄 cvmx-tra.h(34.28 KB)
📄 cvmx-trax-defs.h(197.09 KB)
📄 cvmx-twsi.c(16.25 KB)
📄 cvmx-twsi.h(10.22 KB)
📄 cvmx-uahcx-defs.h(181.38 KB)
📄 cvmx-uart.c(5.69 KB)
📄 cvmx-uart.h(4.58 KB)
📄 cvmx-uctlx-defs.h(50.26 KB)
📄 cvmx-usb.c(138.53 KB)
📄 cvmx-usb.h(46.67 KB)
📄 cvmx-usbcx-defs.h(259.23 KB)
📄 cvmx-usbd.c(36.09 KB)
📄 cvmx-usbd.h(9.82 KB)
📄 cvmx-usbnx-defs.h(136.12 KB)
📄 cvmx-utils.h(7.54 KB)
📄 cvmx-version.h(2.23 KB)
📄 cvmx-warn.c(2.75 KB)
📄 cvmx-warn.h(2.43 KB)
📄 cvmx-wqe.h(38.61 KB)
📄 cvmx-zip-defs.h(43.18 KB)
📄 cvmx-zip.c(7.37 KB)
📄 cvmx-zip.h(8.5 KB)
📄 cvmx-zone.c(4.7 KB)
📄 cvmx.h(3.5 KB)
📄 octeon-boot-info.h(8.08 KB)
📄 octeon-feature.c(4.71 KB)
📄 octeon-feature.h(11.94 KB)
📄 octeon-model.c(15.79 KB)
📄 octeon-model.h(16.53 KB)
📄 octeon-pci-console.c(19.73 KB)
📄 octeon-pci-console.h(5.18 KB)

Editing: cvmx-mgmt-port.c

/***********************license start***************
 * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
 * reserved.
 *
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met:
 *
 *   * Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *
 *   * Redistributions in binary form must reproduce the above
 *     copyright notice, this list of conditions and the following
 *     disclaimer in the documentation and/or other materials provided
 *     with the distribution.

*   * Neither the name of Cavium Inc. nor the names of
 *     its contributors may be used to endorse or promote products
 *     derived from this software without specific prior written
 *     permission.

* This Software, including technical data, may be subject to U.S. export  control
 * laws, including the U.S. Export Administration Act and its  associated
 * regulations, and may be subject to export or import  regulations in other
 * countries.

* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
 ***********************license end**************************************/

/**
 * @file
 *
 * Support functions for managing the MII management port
 *
 * <hr>$Revision: 70030 $<hr>
 */
#include "cvmx.h"
#include "cvmx-bootmem.h"
#include "cvmx-spinlock.h"
#include "cvmx-mdio.h"
#include "cvmx-mgmt-port.h"
#include "cvmx-sysinfo.h"
#if !defined(CVMX_BUILD_FOR_FREEBSD_KERNEL)
#include "cvmx-error.h"
#endif

/**
 * Enum of MIX interface modes
 */
typedef enum
{
    CVMX_MGMT_PORT_NONE = 0,
    CVMX_MGMT_PORT_MII_MODE,
    CVMX_MGMT_PORT_RGMII_MODE,
} cvmx_mgmt_port_mode_t;

/**
 * Format of the TX/RX ring buffer entries
 */
typedef union
{
    uint64_t u64;
    struct
    {
        uint64_t    reserved_62_63  : 2;
        uint64_t    len             : 14;   /* Length of the buffer/packet in bytes */
        uint64_t    tstamp          : 1;    /* For TX, signals that the packet should be timestamped */
        uint64_t    code            : 7;    /* The RX error code */
        uint64_t    addr            : 40;   /* Physical address of the buffer */
    } s;
} cvmx_mgmt_port_ring_entry_t;

/**
 * Per port state required for each mgmt port
 */
typedef struct
{
    cvmx_spinlock_t             lock;           /* Used for exclusive access to this structure */
    int                         tx_write_index; /* Where the next TX will write in the tx_ring and tx_buffers */
    int                         rx_read_index;  /* Where the next RX will be in the rx_ring and rx_buffers */
    int                         port;           /* Port to use.  (This is the 'fake' IPD port number */
    uint64_t                    mac;            /* Our MAC address */
    cvmx_mgmt_port_ring_entry_t tx_ring[CVMX_MGMT_PORT_NUM_TX_BUFFERS];
    cvmx_mgmt_port_ring_entry_t rx_ring[CVMX_MGMT_PORT_NUM_RX_BUFFERS];
    char                        tx_buffers[CVMX_MGMT_PORT_NUM_TX_BUFFERS][CVMX_MGMT_PORT_TX_BUFFER_SIZE];
    char                        rx_buffers[CVMX_MGMT_PORT_NUM_RX_BUFFERS][CVMX_MGMT_PORT_RX_BUFFER_SIZE];
    cvmx_mgmt_port_mode_t       mode;          /* Mode of the interface */
} cvmx_mgmt_port_state_t;

/**
 * Pointers to each mgmt port's state
 */
CVMX_SHARED cvmx_mgmt_port_state_t *cvmx_mgmt_port_state_ptr = NULL;

/**
 * Return the number of management ports supported by this chip
 *
 * @return Number of ports
 */
static int __cvmx_mgmt_port_num_ports(void)
{
#if defined(OCTEON_VENDOR_GEFES)
    return 0; /* none of the GEFES boards have mgmt ports */
#else
    if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))
        return 1;
    else if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN6XXX))
        return 2;
    else
        return 0;
#endif
}

/**
 * Return the number of management ports supported on this board.
 *
 * @return Number of ports
 */
int cvmx_mgmt_port_num_ports(void)
{
    return __cvmx_mgmt_port_num_ports();
}

/**
 * Called to initialize a management port for use. Multiple calls
 * to this function across applications is safe.
 *
 * @param port   Port to initialize
 *
 * @return CVMX_MGMT_PORT_SUCCESS or an error code
 */
cvmx_mgmt_port_result_t cvmx_mgmt_port_initialize(int port)
{
    char *alloc_name = "cvmx_mgmt_port";
    cvmx_mixx_oring1_t oring1;
    cvmx_mixx_ctl_t mix_ctl;

if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports()))
        return CVMX_MGMT_PORT_INVALID_PARAM;

cvmx_mgmt_port_state_ptr = cvmx_bootmem_alloc_named_flags(CVMX_MGMT_PORT_NUM_PORTS * sizeof(cvmx_mgmt_port_state_t), 128, alloc_name, CVMX_BOOTMEM_FLAG_END_ALLOC);
    if (cvmx_mgmt_port_state_ptr)
    {
        memset(cvmx_mgmt_port_state_ptr, 0, CVMX_MGMT_PORT_NUM_PORTS * sizeof(cvmx_mgmt_port_state_t));
    }
    else
    {
        const cvmx_bootmem_named_block_desc_t *block_desc = cvmx_bootmem_find_named_block(alloc_name);
        if (block_desc)
            cvmx_mgmt_port_state_ptr = cvmx_phys_to_ptr(block_desc->base_addr);
        else
        {
            cvmx_dprintf("ERROR: cvmx_mgmt_port_initialize: Unable to get named block %s on MIX%d.\n", alloc_name, port);
            return CVMX_MGMT_PORT_NO_MEMORY;
        }
    }

/* Reset the MIX block if the previous user had a different TX ring size, or if
    ** we allocated a new (and blank) state structure. */
    mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port));
    if (!mix_ctl.s.reset)
    {
        oring1.u64 = cvmx_read_csr(CVMX_MIXX_ORING1(port));
        if (oring1.s.osize != CVMX_MGMT_PORT_NUM_TX_BUFFERS || cvmx_mgmt_port_state_ptr[port].tx_ring[0].u64 == 0)
        {
            mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port));
            mix_ctl.s.en = 0;
            cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64);
            do
            {
                mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port));
            } while (mix_ctl.s.busy);
            mix_ctl.s.reset = 1;
            cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64);
            cvmx_read_csr(CVMX_MIXX_CTL(port));
            memset(cvmx_mgmt_port_state_ptr + port, 0, sizeof(cvmx_mgmt_port_state_t));
        }
    }

if (cvmx_mgmt_port_state_ptr[port].tx_ring[0].u64 == 0)
    {
        cvmx_mgmt_port_state_t *state = cvmx_mgmt_port_state_ptr + port;
        int i;
        cvmx_mixx_bist_t mix_bist;
        cvmx_agl_gmx_bist_t agl_gmx_bist;
        cvmx_mixx_oring1_t oring1;
        cvmx_mixx_iring1_t iring1;
        cvmx_mixx_ctl_t mix_ctl;
        cvmx_agl_prtx_ctl_t agl_prtx_ctl;

/* Make sure BIST passed */
        mix_bist.u64 = cvmx_read_csr(CVMX_MIXX_BIST(port));
        if (mix_bist.u64)
            cvmx_dprintf("WARNING: cvmx_mgmt_port_initialize: Managment port MIX failed BIST (0x%016llx) on MIX%d\n", CAST64(mix_bist.u64), port);

agl_gmx_bist.u64 = cvmx_read_csr(CVMX_AGL_GMX_BIST);
        if (agl_gmx_bist.u64)
            cvmx_dprintf("WARNING: cvmx_mgmt_port_initialize: Managment port AGL failed BIST (0x%016llx) on MIX%d\n", CAST64(agl_gmx_bist.u64), port);

/* Clear all state information */
        memset(state, 0, sizeof(*state));

/* Take the control logic out of reset */
        mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port));
        mix_ctl.s.reset = 0;
        cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64);

/* Read until reset == 0.  Timeout should never happen... */
        if (CVMX_WAIT_FOR_FIELD64(CVMX_MIXX_CTL(port), cvmx_mixx_ctl_t, reset, ==, 0, 300000000))
        {
            cvmx_dprintf("ERROR: cvmx_mgmt_port_initialize: Timeout waiting for MIX(%d) reset.\n", port);
            return CVMX_MGMT_PORT_INIT_ERROR;
        }

/* Set the PHY address and mode of the interface (RGMII/MII mode). */
        if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
        {
            state->port = -1;
            state->mode = CVMX_MGMT_PORT_MII_MODE;
        }
        else
        {
            int port_num = CVMX_HELPER_BOARD_MGMT_IPD_PORT + port;
            int phy_addr = cvmx_helper_board_get_mii_address(port_num);
            if (phy_addr != -1)
            {
                cvmx_mdio_phy_reg_status_t phy_status;
                /* Read PHY status register to find the mode of the interface. */
                phy_status.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_STATUS);
                if (phy_status.s.capable_extended_status == 0) // MII mode
                    state->mode = CVMX_MGMT_PORT_MII_MODE;
                else if (OCTEON_IS_MODEL(OCTEON_CN6XXX)
                         && phy_status.s.capable_extended_status) // RGMII mode
                    state->mode = CVMX_MGMT_PORT_RGMII_MODE;
                else
                    state->mode = CVMX_MGMT_PORT_NONE;
            }
            else
            {
                cvmx_dprintf("ERROR: cvmx_mgmt_port_initialize: Not able to read the PHY on MIX%d\n", port);
                return CVMX_MGMT_PORT_INVALID_PARAM;
            }
            state->port = port_num;
        }

/* All interfaces should be configured in same mode */
        for (i = 0; i < __cvmx_mgmt_port_num_ports(); i++)
        {
            if (i != port
                && cvmx_mgmt_port_state_ptr[i].mode != CVMX_MGMT_PORT_NONE
                && cvmx_mgmt_port_state_ptr[i].mode != state->mode)
            {
                cvmx_dprintf("ERROR: cvmx_mgmt_port_initialize: All ports in MIX interface are not configured in same mode.\n \
	Port %d is configured as %d\n \
	And Port %d is configured as %d\n", port, state->mode, i, cvmx_mgmt_port_state_ptr[i].mode);
                return CVMX_MGMT_PORT_INVALID_PARAM;
            }
        }

/* Create a default MAC address */
        state->mac = 0x000000dead000000ull;
        state->mac += 0xffffff & CAST64(state);

/* Setup the TX ring */
        for (i=0; i<CVMX_MGMT_PORT_NUM_TX_BUFFERS; i++)
        {
            state->tx_ring[i].s.len = CVMX_MGMT_PORT_TX_BUFFER_SIZE;
            state->tx_ring[i].s.addr = cvmx_ptr_to_phys(state->tx_buffers[i]);
        }

/* Tell the HW where the TX ring is */
        oring1.u64 = 0;
        oring1.s.obase = cvmx_ptr_to_phys(state->tx_ring)>>3;
        oring1.s.osize = CVMX_MGMT_PORT_NUM_TX_BUFFERS;
        CVMX_SYNCWS;
        cvmx_write_csr(CVMX_MIXX_ORING1(port), oring1.u64);

/* Setup the RX ring */
        for (i=0; i<CVMX_MGMT_PORT_NUM_RX_BUFFERS; i++)
        {
            /* This size is -8 due to an errata for CN56XX pass 1 */
            state->rx_ring[i].s.len = CVMX_MGMT_PORT_RX_BUFFER_SIZE - 8;
            state->rx_ring[i].s.addr = cvmx_ptr_to_phys(state->rx_buffers[i]);
        }

/* Tell the HW where the RX ring is */
        iring1.u64 = 0;
        iring1.s.ibase = cvmx_ptr_to_phys(state->rx_ring)>>3;
        iring1.s.isize = CVMX_MGMT_PORT_NUM_RX_BUFFERS;
        CVMX_SYNCWS;
        cvmx_write_csr(CVMX_MIXX_IRING1(port), iring1.u64);
        cvmx_write_csr(CVMX_MIXX_IRING2(port), CVMX_MGMT_PORT_NUM_RX_BUFFERS);

/* Disable the external input/output */
        cvmx_mgmt_port_disable(port);

/* Set the MAC address filtering up */
        cvmx_mgmt_port_set_mac(port, state->mac);

/* Set the default max size to an MTU of 1500 with L2 and VLAN */
        cvmx_mgmt_port_set_max_packet_size(port, 1518);

/* Enable the port HW. Packets are not allowed until cvmx_mgmt_port_enable() is called */
        mix_ctl.u64 = 0;
        mix_ctl.s.crc_strip = 1;    /* Strip the ending CRC */
        mix_ctl.s.en = 1;           /* Enable the port */
        mix_ctl.s.nbtarb = 0;       /* Arbitration mode */
        mix_ctl.s.mrq_hwm = 1;      /* MII CB-request FIFO programmable high watermark */
        cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64);

/* Select the mode of operation for the interface. */
        if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
        {
            agl_prtx_ctl.u64 = cvmx_read_csr(CVMX_AGL_PRTX_CTL(port));

if (state->mode == CVMX_MGMT_PORT_RGMII_MODE)
                agl_prtx_ctl.s.mode = 0;
            else if (state->mode == CVMX_MGMT_PORT_MII_MODE)
                agl_prtx_ctl.s.mode = 1;
            else
            {
                cvmx_dprintf("ERROR: cvmx_mgmt_port_initialize: Invalid mode for MIX(%d)\n", port);
                return CVMX_MGMT_PORT_INVALID_PARAM;
            }

cvmx_write_csr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64);
	}

/* Initialize the physical layer. */
        if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
        {
            /* MII clocks counts are based on the 125Mhz reference, so our
                delays need to be scaled to match the core clock rate. The
                "+1" is to make sure rounding always waits a little too
                long. */
            uint64_t clock_scale = cvmx_clock_get_rate(CVMX_CLOCK_CORE) / 125000000 + 1;

/* Take the DLL and clock tree out of reset */
            agl_prtx_ctl.u64 = cvmx_read_csr(CVMX_AGL_PRTX_CTL(port));
            agl_prtx_ctl.s.clkrst = 0;
            if (state->mode == CVMX_MGMT_PORT_RGMII_MODE) // RGMII Initialization
            {
                agl_prtx_ctl.s.dllrst = 0;
                agl_prtx_ctl.s.clktx_byp = 0;
            }
            cvmx_write_csr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64);
            cvmx_read_csr(CVMX_AGL_PRTX_CTL(port));  /* Force write out before wait */

/* Wait for the DLL to lock.  External 125 MHz reference clock must be stable at this point. */
            cvmx_wait(256 * clock_scale);

/* The rest of the config is common between RGMII/MII */

/* Enable the interface */
            agl_prtx_ctl.u64 = cvmx_read_csr(CVMX_AGL_PRTX_CTL(port));
            agl_prtx_ctl.s.enable = 1;
            cvmx_write_csr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64);

/* Read the value back to force the previous write */
            agl_prtx_ctl.u64 = cvmx_read_csr(CVMX_AGL_PRTX_CTL(port));

/* Enable the componsation controller */
            agl_prtx_ctl.s.comp = 1;
            agl_prtx_ctl.s.drv_byp = 0;
            cvmx_write_csr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64);
            cvmx_read_csr(CVMX_AGL_PRTX_CTL(port));  /* Force write out before wait */
            cvmx_wait(1024 * clock_scale); // for componsation state to lock.
        }
        else if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X))
        {
            /* Force compensation values, as they are not determined properly by HW */
            cvmx_agl_gmx_drv_ctl_t drv_ctl;

drv_ctl.u64 = cvmx_read_csr(CVMX_AGL_GMX_DRV_CTL);
            if (port)
            {
                drv_ctl.s.byp_en1 = 1;
                drv_ctl.s.nctl1 = 6;
                drv_ctl.s.pctl1 = 6;
            }
            else
            {
                drv_ctl.s.byp_en = 1;
                drv_ctl.s.nctl = 6;
                drv_ctl.s.pctl = 6;
            }
            cvmx_write_csr(CVMX_AGL_GMX_DRV_CTL, drv_ctl.u64);
        }
    }
#if !defined(CVMX_BUILD_FOR_FREEBSD_KERNEL)
    cvmx_error_enable_group(CVMX_ERROR_GROUP_MGMT_PORT, port);
#endif
    return CVMX_MGMT_PORT_SUCCESS;
}

/**
 * Shutdown a management port. This currently disables packet IO
 * but leaves all hardware and buffers. Another application can then
 * call initialize() without redoing the hardware setup.
 *
 * @param port   Management port
 *
 * @return CVMX_MGMT_PORT_SUCCESS or an error code
 */
cvmx_mgmt_port_result_t cvmx_mgmt_port_shutdown(int port)
{
    if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports()))
        return CVMX_MGMT_PORT_INVALID_PARAM;

#if !defined(CVMX_BUILD_FOR_FREEBSD_KERNEL)
    cvmx_error_disable_group(CVMX_ERROR_GROUP_MGMT_PORT, port);
#endif

/* Stop packets from comming in */
    cvmx_mgmt_port_disable(port);

/* We don't free any memory so the next intialize can reuse the HW setup */
    return CVMX_MGMT_PORT_SUCCESS;
}

/**
 * Enable packet IO on a management port
 *
 * @param port   Management port
 *
 * @return CVMX_MGMT_PORT_SUCCESS or an error code
 */
cvmx_mgmt_port_result_t cvmx_mgmt_port_enable(int port)
{
    cvmx_mgmt_port_state_t *state;
    cvmx_agl_gmx_inf_mode_t agl_gmx_inf_mode;
    cvmx_agl_gmx_rxx_frm_ctl_t rxx_frm_ctl;

if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports()))
        return CVMX_MGMT_PORT_INVALID_PARAM;

state = cvmx_mgmt_port_state_ptr + port;

cvmx_spinlock_lock(&state->lock);

rxx_frm_ctl.u64 = 0;
    rxx_frm_ctl.s.pre_align = 1;
    rxx_frm_ctl.s.pad_len = 1;  /* When set, disables the length check for non-min sized pkts with padding in the client data */
    rxx_frm_ctl.s.vlan_len = 1; /* When set, disables the length check for VLAN pkts */
    rxx_frm_ctl.s.pre_free = 1; /* When set, PREAMBLE checking is  less strict */
    rxx_frm_ctl.s.ctl_smac = 0; /* Control Pause Frames can match station SMAC */
    rxx_frm_ctl.s.ctl_mcst = 1; /* Control Pause Frames can match globally assign Multicast address */
    rxx_frm_ctl.s.ctl_bck = 1;  /* Forward pause information to TX block */
    rxx_frm_ctl.s.ctl_drp = 1;  /* Drop Control Pause Frames */
    rxx_frm_ctl.s.pre_strp = 1; /* Strip off the preamble */
    rxx_frm_ctl.s.pre_chk = 1;  /* This port is configured to send PREAMBLE+SFD to begin every frame.  GMX checks that the PREAMBLE is sent correctly */
    cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_CTL(port), rxx_frm_ctl.u64);

/* Enable the AGL block */
    if (OCTEON_IS_MODEL(OCTEON_CN5XXX))
    {
        agl_gmx_inf_mode.u64 = 0;
        agl_gmx_inf_mode.s.en = 1;
        cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64);
    }

/* Configure the port duplex and enables */
    cvmx_mgmt_port_link_set(port, cvmx_mgmt_port_link_get(port));

cvmx_spinlock_unlock(&state->lock);
    return CVMX_MGMT_PORT_SUCCESS;
}

/**
 * Disable packet IO on a management port
 *
 * @param port   Management port
 *
 * @return CVMX_MGMT_PORT_SUCCESS or an error code
 */
cvmx_mgmt_port_result_t cvmx_mgmt_port_disable(int port)
{
    cvmx_mgmt_port_state_t *state;
    cvmx_agl_gmx_prtx_cfg_t agl_gmx_prtx;

if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports()))
        return CVMX_MGMT_PORT_INVALID_PARAM;

state = cvmx_mgmt_port_state_ptr + port;

cvmx_spinlock_lock(&state->lock);

agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
    agl_gmx_prtx.s.en = 0;
    cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);

cvmx_spinlock_unlock(&state->lock);
    return CVMX_MGMT_PORT_SUCCESS;
}

/**
 * Send a packet out the management port. The packet is copied so
 * the input buffer isn't used after this call.
 *
 * @param port       Management port
 * @param packet_len Length of the packet to send. It does not include the final CRC
 * @param buffer     Packet data
 *
 * @return CVMX_MGMT_PORT_SUCCESS or an error code
 */
cvmx_mgmt_port_result_t cvmx_mgmt_port_send(int port, int packet_len, void *buffer)
{
    cvmx_mgmt_port_state_t *state;
    cvmx_mixx_oring2_t mix_oring2;

if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports()))
        return CVMX_MGMT_PORT_INVALID_PARAM;

/* Max sure the packet size is valid */
    if ((packet_len < 1) || (packet_len > CVMX_MGMT_PORT_TX_BUFFER_SIZE))
        return CVMX_MGMT_PORT_INVALID_PARAM;

if (buffer == NULL)
        return CVMX_MGMT_PORT_INVALID_PARAM;

state = cvmx_mgmt_port_state_ptr + port;

cvmx_spinlock_lock(&state->lock);

mix_oring2.u64 = cvmx_read_csr(CVMX_MIXX_ORING2(port));
    if (mix_oring2.s.odbell >= CVMX_MGMT_PORT_NUM_TX_BUFFERS - 1)
    {
        /* No room for another packet */
        cvmx_spinlock_unlock(&state->lock);
        return CVMX_MGMT_PORT_NO_MEMORY;
    }
    else
    {
        /* Copy the packet into the output buffer */
        memcpy(state->tx_buffers[state->tx_write_index], buffer, packet_len);
        /* Insert the source MAC */
        memcpy(state->tx_buffers[state->tx_write_index] + 6, ((char*)&state->mac) + 2, 6);
        /* Update the TX ring buffer entry size */
        state->tx_ring[state->tx_write_index].s.len = packet_len;
        /* This code doesn't support TX timestamps */
        state->tx_ring[state->tx_write_index].s.tstamp = 0;
        /* Increment our TX index */
        state->tx_write_index = (state->tx_write_index + 1) % CVMX_MGMT_PORT_NUM_TX_BUFFERS;
        /* Ring the doorbell, sending the packet */
        CVMX_SYNCWS;
        cvmx_write_csr(CVMX_MIXX_ORING2(port), 1);
        if (cvmx_read_csr(CVMX_MIXX_ORCNT(port)))
            cvmx_write_csr(CVMX_MIXX_ORCNT(port), cvmx_read_csr(CVMX_MIXX_ORCNT(port)));

cvmx_spinlock_unlock(&state->lock);
        return CVMX_MGMT_PORT_SUCCESS;
    }
}

#if defined(__FreeBSD__)
/**
 * Send a packet out the management port. The packet is copied so
 * the input mbuf isn't used after this call.
 *
 * @param port       Management port
 * @param m          Packet mbuf (with pkthdr)
 *
 * @return CVMX_MGMT_PORT_SUCCESS or an error code
 */
cvmx_mgmt_port_result_t cvmx_mgmt_port_sendm(int port, const struct mbuf *m)
{
    cvmx_mgmt_port_state_t *state;
    cvmx_mixx_oring2_t mix_oring2;

if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports()))
        return CVMX_MGMT_PORT_INVALID_PARAM;

/* Max sure the packet size is valid */
    if ((m->m_pkthdr.len < 1) || (m->m_pkthdr.len > CVMX_MGMT_PORT_TX_BUFFER_SIZE))
        return CVMX_MGMT_PORT_INVALID_PARAM;

state = cvmx_mgmt_port_state_ptr + port;

cvmx_spinlock_lock(&state->lock);

mix_oring2.u64 = cvmx_read_csr(CVMX_MIXX_ORING2(port));
    if (mix_oring2.s.odbell >= CVMX_MGMT_PORT_NUM_TX_BUFFERS - 1)
    {
        /* No room for another packet */
        cvmx_spinlock_unlock(&state->lock);
        return CVMX_MGMT_PORT_NO_MEMORY;
    }
    else
    {
        /* Copy the packet into the output buffer */
	m_copydata(m, 0, m->m_pkthdr.len, state->tx_buffers[state->tx_write_index]);
        /* Update the TX ring buffer entry size */
        state->tx_ring[state->tx_write_index].s.len = m->m_pkthdr.len;
        /* This code doesn't support TX timestamps */
        state->tx_ring[state->tx_write_index].s.tstamp = 0;
        /* Increment our TX index */
        state->tx_write_index = (state->tx_write_index + 1) % CVMX_MGMT_PORT_NUM_TX_BUFFERS;
        /* Ring the doorbell, sending the packet */
        CVMX_SYNCWS;
        cvmx_write_csr(CVMX_MIXX_ORING2(port), 1);
        if (cvmx_read_csr(CVMX_MIXX_ORCNT(port)))
            cvmx_write_csr(CVMX_MIXX_ORCNT(port), cvmx_read_csr(CVMX_MIXX_ORCNT(port)));

cvmx_spinlock_unlock(&state->lock);
        return CVMX_MGMT_PORT_SUCCESS;
    }
}
#endif

/**
 * Receive a packet from the management port.
 *
 * @param port       Management port
 * @param buffer_len Size of the buffer to receive the packet into
 * @param buffer     Buffer to receive the packet into
 *
 * @return The size of the packet, or a negative erorr code on failure. Zero
 *         means that no packets were available.
 */
int cvmx_mgmt_port_receive(int port, int buffer_len, uint8_t *buffer)
{
    cvmx_mixx_ircnt_t mix_ircnt;
    cvmx_mgmt_port_state_t *state;
    int result;

if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports()))
        return CVMX_MGMT_PORT_INVALID_PARAM;

/* Max sure the buffer size is valid */
    if (buffer_len < 1)
        return CVMX_MGMT_PORT_INVALID_PARAM;

if (buffer == NULL)
        return CVMX_MGMT_PORT_INVALID_PARAM;

state = cvmx_mgmt_port_state_ptr + port;

cvmx_spinlock_lock(&state->lock);

/* Find out how many RX packets are pending */
    mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port));
    if (mix_ircnt.s.ircnt)
    {
        uint64_t *source = (void *)state->rx_buffers[state->rx_read_index];
	uint64_t *zero_check = source;
        /* CN56XX pass 1 has an errata where packets might start 8 bytes
            into the buffer instead of at their correct lcoation. If the
            first 8 bytes is zero we assume this has happened */
        if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) && (*zero_check == 0))
            source++;
        /* Start off with zero bytes received */
        result = 0;
        /* While the completion code signals more data, copy the buffers
            into the user's data */
        while (state->rx_ring[state->rx_read_index].s.code == 16)
        {
            /* Only copy what will fit in the user's buffer */
            int length = state->rx_ring[state->rx_read_index].s.len;
            if (length > buffer_len)
                length = buffer_len;
            memcpy(buffer, source, length);
            /* Reduce the size of the buffer to the remaining space. If we run
                out we will signal an error when the code 15 buffer doesn't fit */
            buffer += length;
            buffer_len -= length;
            result += length;
            /* Update this buffer for reuse in future receives. This size is
                -8 due to an errata for CN56XX pass 1 */
            state->rx_ring[state->rx_read_index].s.code = 0;
            state->rx_ring[state->rx_read_index].s.len = CVMX_MGMT_PORT_RX_BUFFER_SIZE - 8;
            state->rx_read_index = (state->rx_read_index + 1) % CVMX_MGMT_PORT_NUM_RX_BUFFERS;
            /* Zero the beginning of the buffer for use by the errata check */
            *zero_check = 0;
            CVMX_SYNCWS;
            /* Increment the number of RX buffers */
            cvmx_write_csr(CVMX_MIXX_IRING2(port), 1);
            source = (void *)state->rx_buffers[state->rx_read_index];
            zero_check = source;
        }

/* Check for the final good completion code */
        if (state->rx_ring[state->rx_read_index].s.code == 15)
        {
            if (buffer_len >= state->rx_ring[state->rx_read_index].s.len)
            {
                int length = state->rx_ring[state->rx_read_index].s.len;
                memcpy(buffer, source, length);
                result += length;
            }
            else
            {
                /* Not enough room for the packet */
                cvmx_dprintf("ERROR: cvmx_mgmt_port_receive: Packet (%d) larger than supplied buffer (%d)\n", state->rx_ring[state->rx_read_index].s.len, buffer_len);
                result = CVMX_MGMT_PORT_NO_MEMORY;
            }
        }
        else
        {
            cvmx_dprintf("ERROR: cvmx_mgmt_port_receive: Receive error code %d. Packet dropped(Len %d), \n",
                         state->rx_ring[state->rx_read_index].s.code, state->rx_ring[state->rx_read_index].s.len + result);
            result = -state->rx_ring[state->rx_read_index].s.code;

/* Check to see if we need to change the duplex. */
            cvmx_mgmt_port_link_set(port, cvmx_mgmt_port_link_get(port));
        }

/* Clean out the ring buffer entry. This size is -8 due to an errata
            for CN56XX pass 1 */
        state->rx_ring[state->rx_read_index].s.code = 0;
        state->rx_ring[state->rx_read_index].s.len = CVMX_MGMT_PORT_RX_BUFFER_SIZE - 8;
        state->rx_read_index = (state->rx_read_index + 1) % CVMX_MGMT_PORT_NUM_RX_BUFFERS;
        /* Zero the beginning of the buffer for use by the errata check */
        *zero_check = 0;
        CVMX_SYNCWS;
        /* Increment the number of RX buffers */
        cvmx_write_csr(CVMX_MIXX_IRING2(port), 1);
        /* Decrement the pending RX count */
        cvmx_write_csr(CVMX_MIXX_IRCNT(port), 1);
    }
    else
    {
        /* No packets available */
        result = 0;
    }
    cvmx_spinlock_unlock(&state->lock);
    return result;
}

/**
 * Set the MAC address for a management port
 *
 * @param port   Management port
 * @param mac    New MAC address. The lower 6 bytes are used.
 *
 * @return CVMX_MGMT_PORT_SUCCESS or an error code
 */
cvmx_mgmt_port_result_t cvmx_mgmt_port_set_mac(int port, uint64_t mac)
{
    cvmx_mgmt_port_state_t *state;
    cvmx_agl_gmx_rxx_adr_ctl_t agl_gmx_rxx_adr_ctl;

if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports()))
        return CVMX_MGMT_PORT_INVALID_PARAM;

state = cvmx_mgmt_port_state_ptr + port;

cvmx_spinlock_lock(&state->lock);

agl_gmx_rxx_adr_ctl.u64 = 0;
    agl_gmx_rxx_adr_ctl.s.cam_mode = 1; /* Only accept matching MAC addresses */
    agl_gmx_rxx_adr_ctl.s.mcst = 0;     /* Drop multicast */
    agl_gmx_rxx_adr_ctl.s.bcst = 1;     /* Allow broadcast */
    cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CTL(port), agl_gmx_rxx_adr_ctl.u64);

/* Only using one of the CAMs */
    cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM0(port), (mac >> 40) & 0xff);
    cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM1(port), (mac >> 32) & 0xff);
    cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM2(port), (mac >> 24) & 0xff);
    cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM3(port), (mac >> 16) & 0xff);
    cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM4(port), (mac >> 8) & 0xff);
    cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM5(port), (mac >> 0) & 0xff);
    cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port), 1);
    state->mac = mac;

cvmx_spinlock_unlock(&state->lock);
    return CVMX_MGMT_PORT_SUCCESS;
}

/**
 * Get the MAC address for a management port
 *
 * @param port   Management port
 *
 * @return MAC address
 */
uint64_t cvmx_mgmt_port_get_mac(int port)
{
    if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports()))
        return CVMX_MGMT_PORT_INVALID_PARAM;

return cvmx_mgmt_port_state_ptr[port].mac;
}

/**
 * Set the multicast list.
 *
 * @param port   Management port
 * @param flags  Interface flags
 *
 * @return
 */
void cvmx_mgmt_port_set_multicast_list(int port, int flags)
{
    cvmx_mgmt_port_state_t *state;
    cvmx_agl_gmx_rxx_adr_ctl_t agl_gmx_rxx_adr_ctl;

if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports()))
        return;

state = cvmx_mgmt_port_state_ptr + port;

cvmx_spinlock_lock(&state->lock);

agl_gmx_rxx_adr_ctl.u64 = cvmx_read_csr(CVMX_AGL_GMX_RXX_ADR_CTL(port));

/* Allow broadcast MAC addresses */
    if (!agl_gmx_rxx_adr_ctl.s.bcst)
	agl_gmx_rxx_adr_ctl.s.bcst = 1;

if ((flags & CVMX_IFF_ALLMULTI) || (flags & CVMX_IFF_PROMISC))
	agl_gmx_rxx_adr_ctl.s.mcst = 2; /* Force accept multicast packets */
    else
	agl_gmx_rxx_adr_ctl.s.mcst = 1; /* Force reject multicast packets */

if (flags & CVMX_IFF_PROMISC)
	agl_gmx_rxx_adr_ctl.s.cam_mode = 0; /* Reject matches if promisc. Since CAM is shut off, should accept everything */
    else
	agl_gmx_rxx_adr_ctl.s.cam_mode = 1; /* Filter packets based on the CAM */

cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CTL(port), agl_gmx_rxx_adr_ctl.u64);

if (flags & CVMX_IFF_PROMISC)
	cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port), 0);
    else
	cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port), 1);

cvmx_spinlock_unlock(&state->lock);
}

/**
 * Set the maximum packet allowed in. Size is specified
 * including L2 but without FCS. A normal MTU would corespond
 * to 1514 assuming the standard 14 byte L2 header.
 *
 * @param port   Management port
 * @param size_without_fcs
 *               Size in bytes without FCS
 */
void cvmx_mgmt_port_set_max_packet_size(int port, int size_without_fcs)
{
    cvmx_mgmt_port_state_t *state;

if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports()))
        return;

state = cvmx_mgmt_port_state_ptr + port;

cvmx_spinlock_lock(&state->lock);
    cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_MAX(port), size_without_fcs);
    cvmx_write_csr(CVMX_AGL_GMX_RXX_JABBER(port), (size_without_fcs+7) & 0xfff8);
    cvmx_spinlock_unlock(&state->lock);
}

/**
 * Return the link state of an RGMII/MII port as returned by
 * auto negotiation. The result of this function may not match
 * Octeon's link config if auto negotiation has changed since
 * the last call to cvmx_mgmt_port_link_set().
 *
 * @param port     The RGMII/MII interface port to query
 *
 * @return Link state
 */
cvmx_helper_link_info_t cvmx_mgmt_port_link_get(int port)
{
    cvmx_mgmt_port_state_t *state;
    cvmx_helper_link_info_t result;

state = cvmx_mgmt_port_state_ptr + port;
    result.u64 = 0;

if (port > __cvmx_mgmt_port_num_ports())
    {
        cvmx_dprintf("WARNING: Invalid port %d\n", port);
        return result;
    }

if (state->port != -1)
        return __cvmx_helper_board_link_get(state->port);
    else // Simulator does not have PHY, use some defaults.
    {
        result.s.full_duplex = 1;
        result.s.link_up = 1;
        result.s.speed = 100;
        return result;
    }
    return result;
}

/**
 * Configure RGMII/MII port for the specified link state. This
 * function does not influence auto negotiation at the PHY level.
 *
 * @param port      RGMII/MII interface port
 * @param link_info The new link state
 *
 * @return Zero on success, negative on failure
 */
int cvmx_mgmt_port_link_set(int port, cvmx_helper_link_info_t link_info)
{
    cvmx_agl_gmx_prtx_cfg_t agl_gmx_prtx;

/* Disable GMX before we make any changes. */
    agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
    agl_gmx_prtx.s.en = 0;
    agl_gmx_prtx.s.tx_en = 0;
    agl_gmx_prtx.s.rx_en = 0;
    cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);

if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
    {
        uint64_t one_second = cvmx_clock_get_rate(CVMX_CLOCK_CORE);
        /* Wait for GMX to be idle */
        if (CVMX_WAIT_FOR_FIELD64(CVMX_AGL_GMX_PRTX_CFG(port), cvmx_agl_gmx_prtx_cfg_t, rx_idle, ==, 1, one_second)
            || CVMX_WAIT_FOR_FIELD64(CVMX_AGL_GMX_PRTX_CFG(port), cvmx_agl_gmx_prtx_cfg_t, tx_idle, ==, 1, one_second))
        {
            cvmx_dprintf("MIX%d: Timeout waiting for GMX to be idle\n", port);
            return -1;
        }
    }

agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));

/* Set duplex mode */
    if (!link_info.s.link_up)
        agl_gmx_prtx.s.duplex = 1;   /* Force full duplex on down links */
    else
        agl_gmx_prtx.s.duplex = link_info.s.full_duplex;

switch(link_info.s.speed)
    {
        case 10:
            agl_gmx_prtx.s.speed = 0;
            agl_gmx_prtx.s.slottime = 0;
            if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
            {
                agl_gmx_prtx.s.speed_msb = 1;
                agl_gmx_prtx.s.burst = 1;
            }
         break;

case 100:
            agl_gmx_prtx.s.speed = 0;
            agl_gmx_prtx.s.slottime = 0;
            if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
            {
                agl_gmx_prtx.s.speed_msb = 0;
                agl_gmx_prtx.s.burst = 1;
            }
            break;

case 1000:
            /* 1000 MBits is only supported on 6XXX chips */
            if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
            {
                agl_gmx_prtx.s.speed_msb = 0;
                agl_gmx_prtx.s.speed = 1;
                agl_gmx_prtx.s.slottime = 1;  /* Only matters for half-duplex */
                agl_gmx_prtx.s.burst = agl_gmx_prtx.s.duplex;
            }
            break;

/* No link */
        case 0:
        default:
            break;
    }

/* Write the new GMX setting with the port still disabled. */
    cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);

/* Read GMX CFG again to make sure the config is completed. */
    agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));

if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
    {
        cvmx_mgmt_port_state_t *state = cvmx_mgmt_port_state_ptr + port;
        cvmx_agl_gmx_txx_clk_t agl_clk;
        agl_clk.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_CLK(port));
        agl_clk.s.clk_cnt = 1;    /* MII (both speeds) and RGMII 1000 setting */
        if (state->mode == CVMX_MGMT_PORT_RGMII_MODE)
        {
            if (link_info.s.speed == 10)
                agl_clk.s.clk_cnt = 50;
            else if (link_info.s.speed == 100)
                agl_clk.s.clk_cnt = 5;
        }
        cvmx_write_csr(CVMX_AGL_GMX_TXX_CLK(port), agl_clk.u64);
    }

/* Enable transmit and receive ports */
    agl_gmx_prtx.s.tx_en = 1;
    agl_gmx_prtx.s.rx_en = 1;
    cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);

/* Enable the link. */
    agl_gmx_prtx.s.en = 1;
    cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
    return 0;
}

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