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📄 cvmip.h(5.88 KB)
📄 cvmx-abi.h(3.67 KB)
📄 cvmx-access-native.h(26.79 KB)
📄 cvmx-access.h(7.82 KB)
📄 cvmx-address.h(10.26 KB)
📄 cvmx-agl-defs.h(213.66 KB)
📄 cvmx-app-hotplug.c(27.64 KB)
📄 cvmx-app-hotplug.h(5.77 KB)
📄 cvmx-app-init-linux.c(14.29 KB)
📄 cvmx-app-init.c(22.54 KB)
📄 cvmx-app-init.h(19.32 KB)
📄 cvmx-asm.h(39.3 KB)
📄 cvmx-asx0-defs.h(5.19 KB)
📄 cvmx-asxx-defs.h(50.57 KB)
📄 cvmx-atomic.h(21.71 KB)
📄 cvmx-bootloader.h(5.64 KB)
📄 cvmx-bootmem.c(40.91 KB)
📄 cvmx-bootmem.h(18.88 KB)
📄 cvmx-ciu-defs.h(702.5 KB)
📄 cvmx-ciu2-defs.h(487.31 KB)
📄 cvmx-clock.c(4.48 KB)
📄 cvmx-clock.h(4.43 KB)
📄 cvmx-cmd-queue.c(11.84 KB)
📄 cvmx-cmd-queue.h(22 KB)
📄 cvmx-cn3010-evb-hs5.c(6.05 KB)
📄 cvmx-cn3010-evb-hs5.h(2.3 KB)
📄 cvmx-compactflash.c(12.8 KB)
📄 cvmx-compactflash.h(3.05 KB)
📄 cvmx-core.c(5.3 KB)
📄 cvmx-core.h(9.46 KB)
📄 cvmx-coremask.c(4.12 KB)
📄 cvmx-coremask.h(8.11 KB)
📄 cvmx-crypto.c(2.6 KB)
📄 cvmx-crypto.h(2.54 KB)
📄 cvmx-csr-enums.h(8.45 KB)
📄 cvmx-csr-typedefs.h(3.92 KB)
📄 cvmx-csr.h(11.46 KB)
📄 cvmx-dbg-defs.h(6.28 KB)
📄 cvmx-debug-handler.S(7.44 KB)
📄 cvmx-debug-remote.c(3.24 KB)
📄 cvmx-debug-uart.c(7.88 KB)
📄 cvmx-debug.c(55.98 KB)
📄 cvmx-debug.h(22.2 KB)
📄 cvmx-dfa-defs.h(383.08 KB)
📄 cvmx-dfa.c(3.7 KB)
📄 cvmx-dfa.h(34.87 KB)
📄 cvmx-dfm-defs.h(205.93 KB)
📄 cvmx-dma-engine.c(20.25 KB)
📄 cvmx-dma-engine.h(24.06 KB)
📄 cvmx-dpi-defs.h(107.61 KB)
📄 cvmx-ebt3000.c(3.82 KB)
📄 cvmx-ebt3000.h(2.25 KB)
📄 cvmx-endor-defs.h(311.42 KB)
📄 cvmx-eoi-defs.h(26.27 KB)
📄 cvmx-fau.h(20.31 KB)
📄 cvmx-flash.c(22.46 KB)
📄 cvmx-flash.h(3.8 KB)
📄 cvmx-fpa-defs.h(157.78 KB)
📄 cvmx-fpa.c(6.63 KB)
📄 cvmx-fpa.h(10.39 KB)
📄 cvmx-gmx.h(3.07 KB)
📄 cvmx-gmxx-defs.h(505.27 KB)
📄 cvmx-gpio-defs.h(36.89 KB)
📄 cvmx-gpio.h(5.48 KB)
📄 cvmx-helper-board.c(58 KB)
📄 cvmx-helper-board.h(7.82 KB)
📄 cvmx-helper-cfg.c(18.68 KB)
📄 cvmx-helper-cfg.h(8.1 KB)
📄 cvmx-helper-check-defines.h(4.1 KB)
📄 cvmx-helper-errata.c(11.91 KB)
📄 cvmx-helper-errata.h(3.24 KB)
📄 cvmx-helper-fpa.c(8.81 KB)
📄 cvmx-helper-fpa.h(3.21 KB)
📄 cvmx-helper-ilk.c(12.74 KB)
📄 cvmx-helper-ilk.h(3.58 KB)
📄 cvmx-helper-jtag.c(7.05 KB)
📄 cvmx-helper-jtag.h(3.91 KB)
📄 cvmx-helper-loop.c(4.35 KB)
📄 cvmx-helper-loop.h(2.78 KB)
📄 cvmx-helper-npi.c(5.72 KB)
📄 cvmx-helper-npi.h(2.82 KB)
📄 cvmx-helper-rgmii.c(19.12 KB)
📄 cvmx-helper-rgmii.h(4.5 KB)
📄 cvmx-helper-sgmii.c(27.09 KB)
📄 cvmx-helper-sgmii.h(4.3 KB)
📄 cvmx-helper-spi.c(8.4 KB)
📄 cvmx-helper-spi.h(3.68 KB)
📄 cvmx-helper-srio.c(11.58 KB)
📄 cvmx-helper-srio.h(3.6 KB)
📄 cvmx-helper-util.c(25.77 KB)
📄 cvmx-helper-util.h(9.88 KB)
📄 cvmx-helper-xaui.c(16.54 KB)
📄 cvmx-helper-xaui.h(4.29 KB)
📄 cvmx-helper.c(69.71 KB)
📄 cvmx-helper.h(12.7 KB)
📄 cvmx-hfa.c(5.04 KB)
📄 cvmx-hfa.h(10.3 KB)
📄 cvmx-higig.h(23.21 KB)
📄 cvmx-ilk-defs.h(170.31 KB)
📄 cvmx-ilk.c(45.16 KB)
📄 cvmx-ilk.h(5.89 KB)
📄 cvmx-interrupt-handler.S(5.87 KB)
📄 cvmx-interrupt.c(47.42 KB)
📄 cvmx-interrupt.h(8.07 KB)
📄 cvmx-iob-defs.h(89.11 KB)
📄 cvmx-iob1-defs.h(6.8 KB)
📄 cvmx-ipd-defs.h(186.51 KB)
📄 cvmx-ipd.c(12.88 KB)
📄 cvmx-ipd.h(6.3 KB)
📄 cvmx-ixf18201.c(12.8 KB)
📄 cvmx-ixf18201.h(3.54 KB)
📄 cvmx-key-defs.h(11 KB)
📄 cvmx-key.h(3.29 KB)
📄 cvmx-l2c-defs.h(353.27 KB)
📄 cvmx-l2c.c(52.95 KB)
📄 cvmx-l2c.h(19.72 KB)
📄 cvmx-l2d-defs.h(60.71 KB)
📄 cvmx-l2t-defs.h(50.68 KB)
📄 cvmx-led-defs.h(22.68 KB)
📄 cvmx-llm.c(36.51 KB)
📄 cvmx-llm.h(11.72 KB)
📄 cvmx-lmcx-defs.h(532.21 KB)
📄 cvmx-log-arc.S(5.67 KB)
📄 cvmx-log.c(18.26 KB)
📄 cvmx-log.h(4.95 KB)
📁 cvmx-malloc
📄 cvmx-malloc.h(7.2 KB)
📄 cvmx-mdio.h(15.99 KB)
📄 cvmx-mgmt-port.c(36.2 KB)
📄 cvmx-mgmt-port.h(7.23 KB)
📄 cvmx-mio-defs.h(454.14 KB)
📄 cvmx-mixx-defs.h(94.59 KB)
📄 cvmx-mpi-defs.h(33.42 KB)
📄 cvmx-nand.c(76.64 KB)
📄 cvmx-nand.h(26.85 KB)
📄 cvmx-ndf-defs.h(25.53 KB)
📄 cvmx-npei-defs.h(378.19 KB)
📄 cvmx-npi-defs.h(252.36 KB)
📄 cvmx-npi.h(4.69 KB)
📄 cvmx-packet.h(2.94 KB)
📄 cvmx-pci-defs.h(250.53 KB)
📄 cvmx-pci.h(2.37 KB)
📄 cvmx-pcie.c(63 KB)
📄 cvmx-pcie.h(10.08 KB)
📄 cvmx-pcieepx-defs.h(304.49 KB)
📄 cvmx-pciercx-defs.h(284.89 KB)
📄 cvmx-pcm-defs.h(12.34 KB)
📄 cvmx-pcmx-defs.h(46.12 KB)
📄 cvmx-pcsx-defs.h(71.23 KB)
📄 cvmx-pcsxx-defs.h(45.79 KB)
📄 cvmx-pemx-defs.h(68.97 KB)
📄 cvmx-pescx-defs.h(49.92 KB)
📄 cvmx-pexp-defs.h(97.89 KB)
📄 cvmx-pip-defs.h(315.91 KB)
📄 cvmx-pip.h(33.65 KB)
📄 cvmx-pko-defs.h(181.41 KB)
📄 cvmx-pko.c(32 KB)
📄 cvmx-pko.h(31.29 KB)
📄 cvmx-platform.h(7.45 KB)
📄 cvmx-pow-defs.h(93.02 KB)
📄 cvmx-pow.c(32.26 KB)
📄 cvmx-pow.h(100.93 KB)
📄 cvmx-power-throttle.c(7.25 KB)
📄 cvmx-power-throttle.h(3.85 KB)
📄 cvmx-profiler.c(7.81 KB)
📄 cvmx-profiler.h(3.15 KB)
📄 cvmx-qlm-tables.c(35.37 KB)
📄 cvmx-qlm.c(23.41 KB)
📄 cvmx-qlm.h(4.76 KB)
📄 cvmx-rad-defs.h(43.58 KB)
📄 cvmx-raid.c(4.71 KB)
📄 cvmx-raid.h(13.02 KB)
📄 cvmx-resources.config(7.66 KB)
📄 cvmx-rng.h(5.02 KB)
📄 cvmx-rnm-defs.h(13.03 KB)
📄 cvmx-rtc.h(4.21 KB)
📄 cvmx-rwlock.h(5.25 KB)
📄 cvmx-scratch.h(4.76 KB)
📄 cvmx-shared-linux-n32.ld(11.8 KB)
📄 cvmx-shared-linux-o32.ld(10.67 KB)
📄 cvmx-shared-linux.ld(11.77 KB)
📄 cvmx-shmem.c(18.89 KB)
📄 cvmx-shmem.h(4.11 KB)
📄 cvmx-sim-magic.h(5.59 KB)
📄 cvmx-sli-defs.h(312.94 KB)
📄 cvmx-smi-defs.h(4.09 KB)
📄 cvmx-smix-defs.h(21.71 KB)
📄 cvmx-spi.c(24.99 KB)
📄 cvmx-spi.h(10.22 KB)
📄 cvmx-spi4000.c(19.23 KB)
📄 cvmx-spinlock.h(11.73 KB)
📄 cvmx-spx0-defs.h(3.94 KB)
📄 cvmx-spxx-defs.h(62.44 KB)
📄 cvmx-srio.c(63.05 KB)
📄 cvmx-srio.h(26.68 KB)
📄 cvmx-sriomaintx-defs.h(222.52 KB)
📄 cvmx-sriox-defs.h(211.56 KB)
📄 cvmx-srxx-defs.h(14.41 KB)
📄 cvmx-sso-defs.h(87.33 KB)
📄 cvmx-stxx-defs.h(34.02 KB)
📄 cvmx-swap.h(4.11 KB)
📄 cvmx-sysinfo.c(8.78 KB)
📄 cvmx-sysinfo.h(6.45 KB)
📄 cvmx-thunder.c(9.22 KB)
📄 cvmx-thunder.h(4.54 KB)
📄 cvmx-tim-defs.h(58.36 KB)
📄 cvmx-tim.c(10.92 KB)
📄 cvmx-tim.h(12.1 KB)
📄 cvmx-tlb.c(10.12 KB)
📄 cvmx-tlb.h(5.07 KB)
📄 cvmx-tra-defs.h(4.59 KB)
📄 cvmx-tra.c(31.16 KB)
📄 cvmx-tra.h(34.28 KB)
📄 cvmx-trax-defs.h(197.09 KB)
📄 cvmx-twsi.c(16.25 KB)
📄 cvmx-twsi.h(10.22 KB)
📄 cvmx-uahcx-defs.h(181.38 KB)
📄 cvmx-uart.c(5.69 KB)
📄 cvmx-uart.h(4.58 KB)
📄 cvmx-uctlx-defs.h(50.26 KB)
📄 cvmx-usb.c(138.53 KB)
📄 cvmx-usb.h(46.67 KB)
📄 cvmx-usbcx-defs.h(259.23 KB)
📄 cvmx-usbd.c(36.09 KB)
📄 cvmx-usbd.h(9.82 KB)
📄 cvmx-usbnx-defs.h(136.12 KB)
📄 cvmx-utils.h(7.54 KB)
📄 cvmx-version.h(2.23 KB)
📄 cvmx-warn.c(2.75 KB)
📄 cvmx-warn.h(2.43 KB)
📄 cvmx-wqe.h(38.61 KB)
📄 cvmx-zip-defs.h(43.18 KB)
📄 cvmx-zip.c(7.37 KB)
📄 cvmx-zip.h(8.5 KB)
📄 cvmx-zone.c(4.7 KB)
📄 cvmx.h(3.5 KB)
📄 octeon-boot-info.h(8.08 KB)
📄 octeon-feature.c(4.71 KB)
📄 octeon-feature.h(11.94 KB)
📄 octeon-model.c(15.79 KB)
📄 octeon-model.h(16.53 KB)
📄 octeon-pci-console.c(19.73 KB)
📄 octeon-pci-console.h(5.18 KB)

Editing: cvmx-ndf-defs.h

/***********************license start***************
 * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
 * reserved.
 *
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met:
 *
 *   * Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *
 *   * Redistributions in binary form must reproduce the above
 *     copyright notice, this list of conditions and the following
 *     disclaimer in the documentation and/or other materials provided
 *     with the distribution.

*   * Neither the name of Cavium Inc. nor the names of
 *     its contributors may be used to endorse or promote products
 *     derived from this software without specific prior written
 *     permission.

* This Software, including technical data, may be subject to U.S. export  control
 * laws, including the U.S. Export Administration Act and its  associated
 * regulations, and may be subject to export or import  regulations in other
 * countries.

* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
 ***********************license end**************************************/

/**
 * cvmx-ndf-defs.h
 *
 * Configuration and status register (CSR) type definitions for
 * Octeon ndf.
 *
 * This file is auto generated. Do not edit.
 *
 * <hr>$Revision$<hr>
 *
 */
#ifndef __CVMX_NDF_DEFS_H__
#define __CVMX_NDF_DEFS_H__

#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_NDF_BT_PG_INFO CVMX_NDF_BT_PG_INFO_FUNC()
static inline uint64_t CVMX_NDF_BT_PG_INFO_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
		cvmx_warn("CVMX_NDF_BT_PG_INFO not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001070001000018ull);
}
#else
#define CVMX_NDF_BT_PG_INFO (CVMX_ADD_IO_SEG(0x0001070001000018ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_NDF_CMD CVMX_NDF_CMD_FUNC()
static inline uint64_t CVMX_NDF_CMD_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
		cvmx_warn("CVMX_NDF_CMD not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001070001000000ull);
}
#else
#define CVMX_NDF_CMD (CVMX_ADD_IO_SEG(0x0001070001000000ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_NDF_DRBELL CVMX_NDF_DRBELL_FUNC()
static inline uint64_t CVMX_NDF_DRBELL_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
		cvmx_warn("CVMX_NDF_DRBELL not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001070001000030ull);
}
#else
#define CVMX_NDF_DRBELL (CVMX_ADD_IO_SEG(0x0001070001000030ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_NDF_ECC_CNT CVMX_NDF_ECC_CNT_FUNC()
static inline uint64_t CVMX_NDF_ECC_CNT_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
		cvmx_warn("CVMX_NDF_ECC_CNT not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001070001000010ull);
}
#else
#define CVMX_NDF_ECC_CNT (CVMX_ADD_IO_SEG(0x0001070001000010ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_NDF_INT CVMX_NDF_INT_FUNC()
static inline uint64_t CVMX_NDF_INT_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
		cvmx_warn("CVMX_NDF_INT not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001070001000020ull);
}
#else
#define CVMX_NDF_INT (CVMX_ADD_IO_SEG(0x0001070001000020ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_NDF_INT_EN CVMX_NDF_INT_EN_FUNC()
static inline uint64_t CVMX_NDF_INT_EN_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
		cvmx_warn("CVMX_NDF_INT_EN not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001070001000028ull);
}
#else
#define CVMX_NDF_INT_EN (CVMX_ADD_IO_SEG(0x0001070001000028ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_NDF_MISC CVMX_NDF_MISC_FUNC()
static inline uint64_t CVMX_NDF_MISC_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
		cvmx_warn("CVMX_NDF_MISC not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001070001000008ull);
}
#else
#define CVMX_NDF_MISC (CVMX_ADD_IO_SEG(0x0001070001000008ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_NDF_ST_REG CVMX_NDF_ST_REG_FUNC()
static inline uint64_t CVMX_NDF_ST_REG_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
		cvmx_warn("CVMX_NDF_ST_REG not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001070001000038ull);
}
#else
#define CVMX_NDF_ST_REG (CVMX_ADD_IO_SEG(0x0001070001000038ull))
#endif

/**
 * cvmx_ndf_bt_pg_info
 *
 * Notes:
 * NDF_BT_PG_INFO provides page size and number of column plus row address cycles information. SW writes to this CSR
 * during boot from Nand Flash. Additionally SW also writes the multiplier value for timing parameters. This value is
 * used during boot, in the SET_TM_PARAM command. This information is used only by the boot load state machine and is
 * otherwise a don't care, once boot is disabled. Also, boot dma's do not use this value.
 *
 * Bytes per Nand Flash page = 2 ** (SIZE + 1) times 256 bytes.
 * 512, 1k, 2k, 4k, 8k, 16k, 32k and 64k are legal bytes per page values
 *
 * Legal values for ADR_CYC field are 3 through 8. SW CSR writes with a value less than 3 will write a 3 to this
 * field, and a SW CSR write with a value greater than 8, will write an 8 to this field.
 *
 * Like all NDF_... registers, 64-bit operations must be used to access this register
 */
union cvmx_ndf_bt_pg_info {
	uint64_t u64;
	struct cvmx_ndf_bt_pg_info_s {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_11_63               : 53;
	uint64_t t_mult                       : 4;  /**< Boot time TIM_MULT[3:0] field of SET__TM_PAR[63:0]
                                                         command */
	uint64_t adr_cyc                      : 4;  /**< # of column address cycles */
	uint64_t size                         : 3;  /**< bytes per page in the nand device */
#else
	uint64_t size                         : 3;
	uint64_t adr_cyc                      : 4;
	uint64_t t_mult                       : 4;
	uint64_t reserved_11_63               : 53;
#endif
	} s;
	struct cvmx_ndf_bt_pg_info_s          cn52xx;
	struct cvmx_ndf_bt_pg_info_s          cn63xx;
	struct cvmx_ndf_bt_pg_info_s          cn63xxp1;
	struct cvmx_ndf_bt_pg_info_s          cn66xx;
	struct cvmx_ndf_bt_pg_info_s          cn68xx;
	struct cvmx_ndf_bt_pg_info_s          cn68xxp1;
};
typedef union cvmx_ndf_bt_pg_info cvmx_ndf_bt_pg_info_t;

/**
 * cvmx_ndf_cmd
 *
 * Notes:
 * When SW reads this csr, RD_VAL bit in NDF_MISC csr is cleared to 0. SW must always write all 8 bytes whenever it writes
 * this csr. If there are fewer than 8 bytes left in the command sequence that SW wants the NAND flash controller to execute, it
 * must insert Idle (WAIT) commands to make up 8 bytes. SW also must ensure there is enough vacancy in the command fifo to accept these
 * 8 bytes, by first reading the FR_BYT field in the NDF_MISC csr.
 *
 * Like all NDF_... registers, 64-bit operations must be used to access this register
 */
union cvmx_ndf_cmd {
	uint64_t u64;
	struct cvmx_ndf_cmd_s {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t nf_cmd                       : 64; /**< 8 Command Bytes */
#else
	uint64_t nf_cmd                       : 64;
#endif
	} s;
	struct cvmx_ndf_cmd_s                 cn52xx;
	struct cvmx_ndf_cmd_s                 cn63xx;
	struct cvmx_ndf_cmd_s                 cn63xxp1;
	struct cvmx_ndf_cmd_s                 cn66xx;
	struct cvmx_ndf_cmd_s                 cn68xx;
	struct cvmx_ndf_cmd_s                 cn68xxp1;
};
typedef union cvmx_ndf_cmd cvmx_ndf_cmd_t;

/**
 * cvmx_ndf_drbell
 *
 * Notes:
 * SW csr writes will increment CNT by the signed 8 bit value being written. SW csr reads return the current CNT value.
 * HW will also modify the value of the CNT field. Everytime HW executes a BUS_ACQ[15:0] command, to arbitrate and win the
 * flash bus, it decrements the CNT field by 1. If the CNT field is already 0 or negative, HW command execution unit will
 * stall when it fetches the new BUS_ACQ[15:0] command, from the command fifo. Only when the SW writes to this CSR with a
 * non-zero data value, can the execution unit come out of the stalled condition, and resume execution.
 *
 * The intended use of this doorbell CSR is to control execution of the Nand Flash commands. The NDF execution unit
 * has to arbitrate for the flash bus, before it can enable a Nand Flash device connected to the Octeon chip, by
 * asserting the device's chip enable. Therefore SW should first load the command fifo, with a full sequence of
 * commands to perform a Nand Flash device task. This command sequence will start with a bus acquire command and
 * the last command in the sequence will be a bus release command. The execution unit will start execution of
 * the sequence only if the [CNT] field is non-zero when it fetches the bus acquire command, which is the first
 * command in this sequence. SW can also, load multiple such sequences, each starting with a chip enable command
 * and ending with a chip disable command, and then write a non-zero data value to this csr to increment the
 * CNT field by the number of the command sequences, loaded to the command fifo.
 *
 * Like all NDF_... registers, 64-bit operations must be used to access this register
 */
union cvmx_ndf_drbell {
	uint64_t u64;
	struct cvmx_ndf_drbell_s {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_8_63                : 56;
	uint64_t cnt                          : 8;  /**< Doorbell count register, 2's complement 8 bit value */
#else
	uint64_t cnt                          : 8;
	uint64_t reserved_8_63                : 56;
#endif
	} s;
	struct cvmx_ndf_drbell_s              cn52xx;
	struct cvmx_ndf_drbell_s              cn63xx;
	struct cvmx_ndf_drbell_s              cn63xxp1;
	struct cvmx_ndf_drbell_s              cn66xx;
	struct cvmx_ndf_drbell_s              cn68xx;
	struct cvmx_ndf_drbell_s              cn68xxp1;
};
typedef union cvmx_ndf_drbell cvmx_ndf_drbell_t;

/**
 * cvmx_ndf_ecc_cnt
 *
 * Notes:
 * XOR_ECC[31:8] = [ecc_gen_byt258, ecc_gen_byt257, ecc_gen_byt256] xor [ecc_258, ecc_257, ecc_256]
 *         ecc_258, ecc_257 and ecc_256 are bytes stored in Nand Flash and read out during boot
 *         ecc_gen_byt258, ecc_gen_byt257, ecc_gen_byt256 are generated from data read out from Nand Flash
 *
 * Like all NDF_... registers, 64-bit operations must be used to access this register
 */
union cvmx_ndf_ecc_cnt {
	uint64_t u64;
	struct cvmx_ndf_ecc_cnt_s {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_32_63               : 32;
	uint64_t xor_ecc                      : 24; /**< result of XOR of ecc read bytes and ecc genarated
                                                         bytes. The value pertains to the last 1 bit ecc err */
	uint64_t ecc_err                      : 8;  /**< Count = \# of 1 bit errors fixed during boot
                                                         This count saturates instead of wrapping around. */
#else
	uint64_t ecc_err                      : 8;
	uint64_t xor_ecc                      : 24;
	uint64_t reserved_32_63               : 32;
#endif
	} s;
	struct cvmx_ndf_ecc_cnt_s             cn52xx;
	struct cvmx_ndf_ecc_cnt_s             cn63xx;
	struct cvmx_ndf_ecc_cnt_s             cn63xxp1;
	struct cvmx_ndf_ecc_cnt_s             cn66xx;
	struct cvmx_ndf_ecc_cnt_s             cn68xx;
	struct cvmx_ndf_ecc_cnt_s             cn68xxp1;
};
typedef union cvmx_ndf_ecc_cnt cvmx_ndf_ecc_cnt_t;

/**
 * cvmx_ndf_int
 *
 * Notes:
 * FULL status is updated when the command fifo becomes full as a result of SW writing a new command to it.
 *
 * EMPTY status is updated when the command fifo becomes empty as a result of command execution unit fetching the
 * last instruction out of the command fifo.
 *
 * Like all NDF_... registers, 64-bit operations must be used to access this register
 */
union cvmx_ndf_int {
	uint64_t u64;
	struct cvmx_ndf_int_s {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_7_63                : 57;
	uint64_t ovrf                         : 1;  /**< NDF_CMD write when fifo is full. Generally a
                                                         fatal error. */
	uint64_t ecc_mult                     : 1;  /**< Multi bit ECC error detected during boot */
	uint64_t ecc_1bit                     : 1;  /**< Single bit ECC error detected and fixed during boot */
	uint64_t sm_bad                       : 1;  /**< One of the state machines in a bad state */
	uint64_t wdog                         : 1;  /**< Watch Dog timer expired during command execution */
	uint64_t full                         : 1;  /**< Command fifo is full */
	uint64_t empty                        : 1;  /**< Command fifo is empty */
#else
	uint64_t empty                        : 1;
	uint64_t full                         : 1;
	uint64_t wdog                         : 1;
	uint64_t sm_bad                       : 1;
	uint64_t ecc_1bit                     : 1;
	uint64_t ecc_mult                     : 1;
	uint64_t ovrf                         : 1;
	uint64_t reserved_7_63                : 57;
#endif
	} s;
	struct cvmx_ndf_int_s                 cn52xx;
	struct cvmx_ndf_int_s                 cn63xx;
	struct cvmx_ndf_int_s                 cn63xxp1;
	struct cvmx_ndf_int_s                 cn66xx;
	struct cvmx_ndf_int_s                 cn68xx;
	struct cvmx_ndf_int_s                 cn68xxp1;
};
typedef union cvmx_ndf_int cvmx_ndf_int_t;

/**
 * cvmx_ndf_int_en
 *
 * Notes:
 * Like all NDF_... registers, 64-bit operations must be used to access this register
 *
 */
union cvmx_ndf_int_en {
	uint64_t u64;
	struct cvmx_ndf_int_en_s {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_7_63                : 57;
	uint64_t ovrf                         : 1;  /**< Wrote to a full command fifo */
	uint64_t ecc_mult                     : 1;  /**< Multi bit ECC error detected during boot */
	uint64_t ecc_1bit                     : 1;  /**< Single bit ECC error detected and fixed during boot */
	uint64_t sm_bad                       : 1;  /**< One of the state machines in a bad state */
	uint64_t wdog                         : 1;  /**< Watch Dog timer expired during command execution */
	uint64_t full                         : 1;  /**< Command fifo is full */
	uint64_t empty                        : 1;  /**< Command fifo is empty */
#else
	uint64_t empty                        : 1;
	uint64_t full                         : 1;
	uint64_t wdog                         : 1;
	uint64_t sm_bad                       : 1;
	uint64_t ecc_1bit                     : 1;
	uint64_t ecc_mult                     : 1;
	uint64_t ovrf                         : 1;
	uint64_t reserved_7_63                : 57;
#endif
	} s;
	struct cvmx_ndf_int_en_s              cn52xx;
	struct cvmx_ndf_int_en_s              cn63xx;
	struct cvmx_ndf_int_en_s              cn63xxp1;
	struct cvmx_ndf_int_en_s              cn66xx;
	struct cvmx_ndf_int_en_s              cn68xx;
	struct cvmx_ndf_int_en_s              cn68xxp1;
};
typedef union cvmx_ndf_int_en cvmx_ndf_int_en_t;

/**
 * cvmx_ndf_misc
 *
 * Notes:
 * NBR_HWM this field specifies the high water mark for the NCB outbound load/store commands receive fifo.
 *   the fifo size is 16 entries.
 *
 * WAIT_CNT this field allows glitch filtering of the WAIT_n input to octeon, from Flash Memory. The count
 *   represents number of eclk cycles.
 *
 * FR_BYT  this field specifies \# of unfilled bytes in the command fifo. Bytes become unfilled as commands
 *   complete execution and exit. (fifo is 256 bytes when BT_DIS=0,  and 1536 bytes when BT_DIS=1)
 *
 * RD_DONE this W1C bit is set to 1 by HW when it reads the last 8 bytes out of the command fifo,
 *   in response to RD_CMD bit being set to 1 by SW.
 *
 * RD_VAL  this read only bit is set to 1 by HW when it reads next 8 bytes from command fifo in response
 *   to RD_CMD bit being set to 1. A SW read of NDF_CMD csr clears this bit to 0.
 *
 * RD_CMD  this R/W bit starts read out from the command fifo, 8 bytes at a time. SW should first read the
 *   RD_VAL bit in  this csr to see if next 8 bytes from the command fifo are available in the
 *   NDF_CMD csr. All command fifo reads start and end on an 8 byte boundary. A RD_CMD in the
 *   middle of command execution will cause the execution to freeze until RD_DONE is set to 1. RD_CMD
 *   bit will be cleared on any NDF_CMD csr write by SW.
 *
 * BT_DMA  this indicates to the NAND flash boot control state machine that boot dma read can begin.
 *   SW should set this bit to 1 after SW has loaded the command fifo. HW sets the bit to 0
 *   when boot dma command execution is complete. If chip enable 0 is not nand flash, this bit is
 *   permanently 1'b0 with SW writes ignored. Whenever BT_DIS=1, this bit will be 0.
 *
 * BT_DIS  this R/W bit indicates to NAND flash boot control state machine that boot operation has ended.
 *   whenever this bit changes from 0 to a 1, the command fifo is emptied as a side effect. This bit must
 *   never be set when booting from nand flash and region zero is enabled.
 *
 * EX_DIS  When 1, command execution stops after completing execution of all commands currently in the command
 *   fifo. Once command execution has stopped, and then new commands are loaded into the command fifo, execution
 *   will not resume as long as this bit is 1. When this bit is 0, command execution will resume if command fifo
 *   is not empty. EX_DIS should be set to 1, during boot i.e. when BT_DIS = 0.
 *
 * RST_FF  reset command fifo to make it empty, any command inflight is not aborted before reseting
 *   the fifo. The fifo comes up empty at the end of power on reset.
 *
 * Like all NDF_... registers, 64-bit operations must be used to access this register
 */
union cvmx_ndf_misc {
	uint64_t u64;
	struct cvmx_ndf_misc_s {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_28_63               : 36;
	uint64_t mb_dis                       : 1;  /**< Disable multibit error hangs and allow boot loads
                                                         or boot dma's proceed as if no multi bit errors
                                                         occured. HW will fix single bit errors as usual */
	uint64_t nbr_hwm                      : 3;  /**< Hi Water mark for NBR fifo or load/stores */
	uint64_t wait_cnt                     : 6;  /**< WAIT input filter count */
	uint64_t fr_byt                       : 11; /**< Number of unfilled Command fifo bytes */
	uint64_t rd_done                      : 1;  /**< This W1C bit is set to 1 by HW when it completes
                                                         command fifo read out, in response to RD_CMD */
	uint64_t rd_val                       : 1;  /**< This RO bit is set to 1 by HW when it reads next 8
                                                         bytes from Command fifo into the NDF_CMD csr
                                                         SW reads NDF_CMD csr, HW clears this bit to 0 */
	uint64_t rd_cmd                       : 1;  /**< When 1, HW reads out contents of the Command fifo 8
                                                         bytes at a time into the NDF_CMD csr */
	uint64_t bt_dma                       : 1;  /**< When set to 1, boot time dma is enabled */
	uint64_t bt_dis                       : 1;  /**< When boot operation is over SW must set to 1
                                                         causes boot state mchines to sleep */
	uint64_t ex_dis                       : 1;  /**< When set to 1, suspends execution of commands at
                                                         next command in the fifo. */
	uint64_t rst_ff                       : 1;  /**< 1=reset command fifo to make it empty,
                                                         0=normal operation */
#else
	uint64_t rst_ff                       : 1;
	uint64_t ex_dis                       : 1;
	uint64_t bt_dis                       : 1;
	uint64_t bt_dma                       : 1;
	uint64_t rd_cmd                       : 1;
	uint64_t rd_val                       : 1;
	uint64_t rd_done                      : 1;
	uint64_t fr_byt                       : 11;
	uint64_t wait_cnt                     : 6;
	uint64_t nbr_hwm                      : 3;
	uint64_t mb_dis                       : 1;
	uint64_t reserved_28_63               : 36;
#endif
	} s;
	struct cvmx_ndf_misc_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_27_63               : 37;
	uint64_t nbr_hwm                      : 3;  /**< Hi Water mark for NBR fifo or load/stores */
	uint64_t wait_cnt                     : 6;  /**< WAIT input filter count */
	uint64_t fr_byt                       : 11; /**< Number of unfilled Command fifo bytes */
	uint64_t rd_done                      : 1;  /**< This W1C bit is set to 1 by HW when it completes
                                                         command fifo read out, in response to RD_CMD */
	uint64_t rd_val                       : 1;  /**< This RO bit is set to 1 by HW when it reads next 8
                                                         bytes from Command fifo into the NDF_CMD csr
                                                         SW reads NDF_CMD csr, HW clears this bit to 0 */
	uint64_t rd_cmd                       : 1;  /**< When 1, HW reads out contents of the Command fifo 8
                                                         bytes at a time into the NDF_CMD csr */
	uint64_t bt_dma                       : 1;  /**< When set to 1, boot time dma is enabled */
	uint64_t bt_dis                       : 1;  /**< When boot operation is over SW must set to 1
                                                         causes boot state mchines to sleep */
	uint64_t ex_dis                       : 1;  /**< When set to 1, suspends execution of commands at
                                                         next command in the fifo. */
	uint64_t rst_ff                       : 1;  /**< 1=reset command fifo to make it empty,
                                                         0=normal operation */
#else
	uint64_t rst_ff                       : 1;
	uint64_t ex_dis                       : 1;
	uint64_t bt_dis                       : 1;
	uint64_t bt_dma                       : 1;
	uint64_t rd_cmd                       : 1;
	uint64_t rd_val                       : 1;
	uint64_t rd_done                      : 1;
	uint64_t fr_byt                       : 11;
	uint64_t wait_cnt                     : 6;
	uint64_t nbr_hwm                      : 3;
	uint64_t reserved_27_63               : 37;
#endif
	} cn52xx;
	struct cvmx_ndf_misc_s                cn63xx;
	struct cvmx_ndf_misc_s                cn63xxp1;
	struct cvmx_ndf_misc_s                cn66xx;
	struct cvmx_ndf_misc_s                cn68xx;
	struct cvmx_ndf_misc_s                cn68xxp1;
};
typedef union cvmx_ndf_misc cvmx_ndf_misc_t;

/**
 * cvmx_ndf_st_reg
 *
 * Notes:
 * This CSR aggregates all state machines used in nand flash controller for debug.
 * Like all NDF_... registers, 64-bit operations must be used to access this register
 */
union cvmx_ndf_st_reg {
	uint64_t u64;
	struct cvmx_ndf_st_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_16_63               : 48;
	uint64_t exe_idle                     : 1;  /**< Command Execution status 1=IDLE, 0=Busy
                                                         1 means execution of command sequence is complete
                                                         and command fifo is empty */
	uint64_t exe_sm                       : 4;  /**< Command Execution State machine states */
	uint64_t bt_sm                        : 4;  /**< Boot load and Boot dma State machine states */
	uint64_t rd_ff_bad                    : 1;  /**< CMD fifo read back State machine in bad state */
	uint64_t rd_ff                        : 2;  /**< CMD fifo read back State machine states */
	uint64_t main_bad                     : 1;  /**< Main State machine in bad state */
	uint64_t main_sm                      : 3;  /**< Main State machine states */
#else
	uint64_t main_sm                      : 3;
	uint64_t main_bad                     : 1;
	uint64_t rd_ff                        : 2;
	uint64_t rd_ff_bad                    : 1;
	uint64_t bt_sm                        : 4;
	uint64_t exe_sm                       : 4;
	uint64_t exe_idle                     : 1;
	uint64_t reserved_16_63               : 48;
#endif
	} s;
	struct cvmx_ndf_st_reg_s              cn52xx;
	struct cvmx_ndf_st_reg_s              cn63xx;
	struct cvmx_ndf_st_reg_s              cn63xxp1;
	struct cvmx_ndf_st_reg_s              cn66xx;
	struct cvmx_ndf_st_reg_s              cn68xx;
	struct cvmx_ndf_st_reg_s              cn68xxp1;
};
typedef union cvmx_ndf_st_reg cvmx_ndf_st_reg_t;

#endif

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