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📄 cvmip.h(5.88 KB)
📄 cvmx-abi.h(3.67 KB)
📄 cvmx-access-native.h(26.79 KB)
📄 cvmx-access.h(7.82 KB)
📄 cvmx-address.h(10.26 KB)
📄 cvmx-agl-defs.h(213.66 KB)
📄 cvmx-app-hotplug.c(27.64 KB)
📄 cvmx-app-hotplug.h(5.77 KB)
📄 cvmx-app-init-linux.c(14.29 KB)
📄 cvmx-app-init.c(22.54 KB)
📄 cvmx-app-init.h(19.32 KB)
📄 cvmx-asm.h(39.3 KB)
📄 cvmx-asx0-defs.h(5.19 KB)
📄 cvmx-asxx-defs.h(50.57 KB)
📄 cvmx-atomic.h(21.71 KB)
📄 cvmx-bootloader.h(5.64 KB)
📄 cvmx-bootmem.c(40.91 KB)
📄 cvmx-bootmem.h(18.88 KB)
📄 cvmx-ciu-defs.h(702.5 KB)
📄 cvmx-ciu2-defs.h(487.31 KB)
📄 cvmx-clock.c(4.48 KB)
📄 cvmx-clock.h(4.43 KB)
📄 cvmx-cmd-queue.c(11.84 KB)
📄 cvmx-cmd-queue.h(22 KB)
📄 cvmx-cn3010-evb-hs5.c(6.05 KB)
📄 cvmx-cn3010-evb-hs5.h(2.3 KB)
📄 cvmx-compactflash.c(12.8 KB)
📄 cvmx-compactflash.h(3.05 KB)
📄 cvmx-core.c(5.3 KB)
📄 cvmx-core.h(9.46 KB)
📄 cvmx-coremask.c(4.12 KB)
📄 cvmx-coremask.h(8.11 KB)
📄 cvmx-crypto.c(2.6 KB)
📄 cvmx-crypto.h(2.54 KB)
📄 cvmx-csr-enums.h(8.45 KB)
📄 cvmx-csr-typedefs.h(3.92 KB)
📄 cvmx-csr.h(11.46 KB)
📄 cvmx-dbg-defs.h(6.28 KB)
📄 cvmx-debug-handler.S(7.44 KB)
📄 cvmx-debug-remote.c(3.24 KB)
📄 cvmx-debug-uart.c(7.88 KB)
📄 cvmx-debug.c(55.98 KB)
📄 cvmx-debug.h(22.2 KB)
📄 cvmx-dfa-defs.h(383.08 KB)
📄 cvmx-dfa.c(3.7 KB)
📄 cvmx-dfa.h(34.87 KB)
📄 cvmx-dfm-defs.h(205.93 KB)
📄 cvmx-dma-engine.c(20.25 KB)
📄 cvmx-dma-engine.h(24.06 KB)
📄 cvmx-dpi-defs.h(107.61 KB)
📄 cvmx-ebt3000.c(3.82 KB)
📄 cvmx-ebt3000.h(2.25 KB)
📄 cvmx-endor-defs.h(311.42 KB)
📄 cvmx-eoi-defs.h(26.27 KB)
📄 cvmx-fau.h(20.31 KB)
📄 cvmx-flash.c(22.46 KB)
📄 cvmx-flash.h(3.8 KB)
📄 cvmx-fpa-defs.h(157.78 KB)
📄 cvmx-fpa.c(6.63 KB)
📄 cvmx-fpa.h(10.39 KB)
📄 cvmx-gmx.h(3.07 KB)
📄 cvmx-gmxx-defs.h(505.27 KB)
📄 cvmx-gpio-defs.h(36.89 KB)
📄 cvmx-gpio.h(5.48 KB)
📄 cvmx-helper-board.c(58 KB)
📄 cvmx-helper-board.h(7.82 KB)
📄 cvmx-helper-cfg.c(18.68 KB)
📄 cvmx-helper-cfg.h(8.1 KB)
📄 cvmx-helper-check-defines.h(4.1 KB)
📄 cvmx-helper-errata.c(11.91 KB)
📄 cvmx-helper-errata.h(3.24 KB)
📄 cvmx-helper-fpa.c(8.81 KB)
📄 cvmx-helper-fpa.h(3.21 KB)
📄 cvmx-helper-ilk.c(12.74 KB)
📄 cvmx-helper-ilk.h(3.58 KB)
📄 cvmx-helper-jtag.c(7.05 KB)
📄 cvmx-helper-jtag.h(3.91 KB)
📄 cvmx-helper-loop.c(4.35 KB)
📄 cvmx-helper-loop.h(2.78 KB)
📄 cvmx-helper-npi.c(5.72 KB)
📄 cvmx-helper-npi.h(2.82 KB)
📄 cvmx-helper-rgmii.c(19.12 KB)
📄 cvmx-helper-rgmii.h(4.5 KB)
📄 cvmx-helper-sgmii.c(27.09 KB)
📄 cvmx-helper-sgmii.h(4.3 KB)
📄 cvmx-helper-spi.c(8.4 KB)
📄 cvmx-helper-spi.h(3.68 KB)
📄 cvmx-helper-srio.c(11.58 KB)
📄 cvmx-helper-srio.h(3.6 KB)
📄 cvmx-helper-util.c(25.77 KB)
📄 cvmx-helper-util.h(9.88 KB)
📄 cvmx-helper-xaui.c(16.54 KB)
📄 cvmx-helper-xaui.h(4.29 KB)
📄 cvmx-helper.c(69.71 KB)
📄 cvmx-helper.h(12.7 KB)
📄 cvmx-hfa.c(5.04 KB)
📄 cvmx-hfa.h(10.3 KB)
📄 cvmx-higig.h(23.21 KB)
📄 cvmx-ilk-defs.h(170.31 KB)
📄 cvmx-ilk.c(45.16 KB)
📄 cvmx-ilk.h(5.89 KB)
📄 cvmx-interrupt-handler.S(5.87 KB)
📄 cvmx-interrupt.c(47.42 KB)
📄 cvmx-interrupt.h(8.07 KB)
📄 cvmx-iob-defs.h(89.11 KB)
📄 cvmx-iob1-defs.h(6.8 KB)
📄 cvmx-ipd-defs.h(186.51 KB)
📄 cvmx-ipd.c(12.88 KB)
📄 cvmx-ipd.h(6.3 KB)
📄 cvmx-ixf18201.c(12.8 KB)
📄 cvmx-ixf18201.h(3.54 KB)
📄 cvmx-key-defs.h(11 KB)
📄 cvmx-key.h(3.29 KB)
📄 cvmx-l2c-defs.h(353.27 KB)
📄 cvmx-l2c.c(52.95 KB)
📄 cvmx-l2c.h(19.72 KB)
📄 cvmx-l2d-defs.h(60.71 KB)
📄 cvmx-l2t-defs.h(50.68 KB)
📄 cvmx-led-defs.h(22.68 KB)
📄 cvmx-llm.c(36.51 KB)
📄 cvmx-llm.h(11.72 KB)
📄 cvmx-lmcx-defs.h(532.21 KB)
📄 cvmx-log-arc.S(5.67 KB)
📄 cvmx-log.c(18.26 KB)
📄 cvmx-log.h(4.95 KB)
📁 cvmx-malloc
📄 cvmx-malloc.h(7.2 KB)
📄 cvmx-mdio.h(15.99 KB)
📄 cvmx-mgmt-port.c(36.2 KB)
📄 cvmx-mgmt-port.h(7.23 KB)
📄 cvmx-mio-defs.h(454.14 KB)
📄 cvmx-mixx-defs.h(94.59 KB)
📄 cvmx-mpi-defs.h(33.42 KB)
📄 cvmx-nand.c(76.64 KB)
📄 cvmx-nand.h(26.85 KB)
📄 cvmx-ndf-defs.h(25.53 KB)
📄 cvmx-npei-defs.h(378.19 KB)
📄 cvmx-npi-defs.h(252.36 KB)
📄 cvmx-npi.h(4.69 KB)
📄 cvmx-packet.h(2.94 KB)
📄 cvmx-pci-defs.h(250.53 KB)
📄 cvmx-pci.h(2.37 KB)
📄 cvmx-pcie.c(63 KB)
📄 cvmx-pcie.h(10.08 KB)
📄 cvmx-pcieepx-defs.h(304.49 KB)
📄 cvmx-pciercx-defs.h(284.89 KB)
📄 cvmx-pcm-defs.h(12.34 KB)
📄 cvmx-pcmx-defs.h(46.12 KB)
📄 cvmx-pcsx-defs.h(71.23 KB)
📄 cvmx-pcsxx-defs.h(45.79 KB)
📄 cvmx-pemx-defs.h(68.97 KB)
📄 cvmx-pescx-defs.h(49.92 KB)
📄 cvmx-pexp-defs.h(97.89 KB)
📄 cvmx-pip-defs.h(315.91 KB)
📄 cvmx-pip.h(33.65 KB)
📄 cvmx-pko-defs.h(181.41 KB)
📄 cvmx-pko.c(32 KB)
📄 cvmx-pko.h(31.29 KB)
📄 cvmx-platform.h(7.45 KB)
📄 cvmx-pow-defs.h(93.02 KB)
📄 cvmx-pow.c(32.26 KB)
📄 cvmx-pow.h(100.93 KB)
📄 cvmx-power-throttle.c(7.25 KB)
📄 cvmx-power-throttle.h(3.85 KB)
📄 cvmx-profiler.c(7.81 KB)
📄 cvmx-profiler.h(3.15 KB)
📄 cvmx-qlm-tables.c(35.37 KB)
📄 cvmx-qlm.c(23.41 KB)
📄 cvmx-qlm.h(4.76 KB)
📄 cvmx-rad-defs.h(43.58 KB)
📄 cvmx-raid.c(4.71 KB)
📄 cvmx-raid.h(13.02 KB)
📄 cvmx-resources.config(7.66 KB)
📄 cvmx-rng.h(5.02 KB)
📄 cvmx-rnm-defs.h(13.03 KB)
📄 cvmx-rtc.h(4.21 KB)
📄 cvmx-rwlock.h(5.25 KB)
📄 cvmx-scratch.h(4.76 KB)
📄 cvmx-shared-linux-n32.ld(11.8 KB)
📄 cvmx-shared-linux-o32.ld(10.67 KB)
📄 cvmx-shared-linux.ld(11.77 KB)
📄 cvmx-shmem.c(18.89 KB)
📄 cvmx-shmem.h(4.11 KB)
📄 cvmx-sim-magic.h(5.59 KB)
📄 cvmx-sli-defs.h(312.94 KB)
📄 cvmx-smi-defs.h(4.09 KB)
📄 cvmx-smix-defs.h(21.71 KB)
📄 cvmx-spi.c(24.99 KB)
📄 cvmx-spi.h(10.22 KB)
📄 cvmx-spi4000.c(19.23 KB)
📄 cvmx-spinlock.h(11.73 KB)
📄 cvmx-spx0-defs.h(3.94 KB)
📄 cvmx-spxx-defs.h(62.44 KB)
📄 cvmx-srio.c(63.05 KB)
📄 cvmx-srio.h(26.68 KB)
📄 cvmx-sriomaintx-defs.h(222.52 KB)
📄 cvmx-sriox-defs.h(211.56 KB)
📄 cvmx-srxx-defs.h(14.41 KB)
📄 cvmx-sso-defs.h(87.33 KB)
📄 cvmx-stxx-defs.h(34.02 KB)
📄 cvmx-swap.h(4.11 KB)
📄 cvmx-sysinfo.c(8.78 KB)
📄 cvmx-sysinfo.h(6.45 KB)
📄 cvmx-thunder.c(9.22 KB)
📄 cvmx-thunder.h(4.54 KB)
📄 cvmx-tim-defs.h(58.36 KB)
📄 cvmx-tim.c(10.92 KB)
📄 cvmx-tim.h(12.1 KB)
📄 cvmx-tlb.c(10.12 KB)
📄 cvmx-tlb.h(5.07 KB)
📄 cvmx-tra-defs.h(4.59 KB)
📄 cvmx-tra.c(31.16 KB)
📄 cvmx-tra.h(34.28 KB)
📄 cvmx-trax-defs.h(197.09 KB)
📄 cvmx-twsi.c(16.25 KB)
📄 cvmx-twsi.h(10.22 KB)
📄 cvmx-uahcx-defs.h(181.38 KB)
📄 cvmx-uart.c(5.69 KB)
📄 cvmx-uart.h(4.58 KB)
📄 cvmx-uctlx-defs.h(50.26 KB)
📄 cvmx-usb.c(138.53 KB)
📄 cvmx-usb.h(46.67 KB)
📄 cvmx-usbcx-defs.h(259.23 KB)
📄 cvmx-usbd.c(36.09 KB)
📄 cvmx-usbd.h(9.82 KB)
📄 cvmx-usbnx-defs.h(136.12 KB)
📄 cvmx-utils.h(7.54 KB)
📄 cvmx-version.h(2.23 KB)
📄 cvmx-warn.c(2.75 KB)
📄 cvmx-warn.h(2.43 KB)
📄 cvmx-wqe.h(38.61 KB)
📄 cvmx-zip-defs.h(43.18 KB)
📄 cvmx-zip.c(7.37 KB)
📄 cvmx-zip.h(8.5 KB)
📄 cvmx-zone.c(4.7 KB)
📄 cvmx.h(3.5 KB)
📄 octeon-boot-info.h(8.08 KB)
📄 octeon-feature.c(4.71 KB)
📄 octeon-feature.h(11.94 KB)
📄 octeon-model.c(15.79 KB)
📄 octeon-model.h(16.53 KB)
📄 octeon-pci-console.c(19.73 KB)
📄 octeon-pci-console.h(5.18 KB)

Editing: cvmx-spi4000.c

/***********************license start***************
 * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
 * reserved.
 *
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met:
 *
 *   * Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *
 *   * Redistributions in binary form must reproduce the above
 *     copyright notice, this list of conditions and the following
 *     disclaimer in the documentation and/or other materials provided
 *     with the distribution.

*   * Neither the name of Cavium Inc. nor the names of
 *     its contributors may be used to endorse or promote products
 *     derived from this software without specific prior written
 *     permission.

* This Software, including technical data, may be subject to U.S. export  control
 * laws, including the U.S. Export Administration Act and its  associated
 * regulations, and may be subject to export or import  regulations in other
 * countries.

* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
 ***********************license end**************************************/

/**
 * @file
 *
 * Support library for the SPI4000 card
 *
 * <hr>$Revision: 70030 $<hr>
 */
#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
#include <linux/module.h>
#include <asm/octeon/cvmx.h>
#include <asm/octeon/cvmx-spi.h>
#include <asm/octeon/cvmx-twsi.h>
#include <asm/octeon/cvmx-gmxx-defs.h>
#else
#include "cvmx.h"
#include "cvmx-spi.h"
#include "cvmx-twsi.h"
#endif

/* If someone is using an old config, make the SPI4000 act like RGMII for backpressure */
#ifndef CVMX_HELPER_DISABLE_SPI4000_BACKPRESSURE
#ifndef CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE
#define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 0
#endif
#define CVMX_HELPER_DISABLE_SPI4000_BACKPRESSURE CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE
#endif

#define SPI4000_READ_ADDRESS_HIGH   0xf0
#define SPI4000_READ_ADDRESS_LOW    0xf1
#define SPI4000_WRITE_ADDRESS_HIGH  0xf2
#define SPI4000_WRITE_ADDRESS_LOW   0xf3
#define SPI4000_READ_DATA0          0xf4    /* High byte */
#define SPI4000_READ_DATA1          0xf5
#define SPI4000_READ_DATA2          0xf6
#define SPI4000_READ_DATA3          0xf7    /* Low byte */
#define SPI4000_WRITE_DATA0         0xf8    /* High byte */
#define SPI4000_WRITE_DATA1         0xf9
#define SPI4000_WRITE_DATA2         0xfa
#define SPI4000_WRITE_DATA3         0xfb    /* Low byte */
#define SPI4000_DO_READ             0xfc    /* Issue a read, returns read status */
#define SPI4000_GET_READ_STATUS     0xfd    /* 0xff: initial state, 2: Read failed, 1: Read pending, 0: Read success */
#define SPI4000_DO_WRITE            0xfe    /* Issue a write, returns write status */
#define SPI4000_GET_WRITE_STATUS    0xff    /* 0xff: initial state, 6: Write failed, 5: Write pending, 4: Write success */
#define SPI4000_TWSI_ID(interface)  (0x66 + interface)

/* MDI Single Command (register 0x680) */
typedef union
{
    uint32_t u32;
    struct
    {
        uint32_t    reserved_21_31  : 11;
        uint32_t    mdi_command     : 1; /**< Performs an MDIO access. When set, this bit
                                            self clears upon completion of the access. */
        uint32_t    reserved_18_19  : 2;
        uint32_t    op_code         : 2; /**< MDIO Op Code
                                            00 = Reserved
                                            01 = Write Access
                                            10 = Read Access
                                            11 = Reserved */
        uint32_t    reserved_13_15  : 3;
        uint32_t    phy_address     : 5; /**< Address of external PHY device */
        uint32_t    reserved_5_7    : 3;
        uint32_t    reg_address     : 5; /**< Address of register within external PHY */
    } s;
} mdio_single_command_t;

static CVMX_SHARED int interface_is_spi4000[2] = {0,0};

/**
 * @INTERNAL
 * Write data to the specified SPI4000 address
 *
 * @param interface Interface the SPI4000 is on. (0 or 1)
 * @param address   Address to write to
 * @param data      Data to write
 */
static void __cvmx_spi4000_write(int interface, int address, uint32_t data)
{
    int status;
    cvmx_twsix_write_ia(0, SPI4000_TWSI_ID(interface), SPI4000_WRITE_ADDRESS_HIGH, 2, 1, address);
    cvmx_twsix_write_ia(0, SPI4000_TWSI_ID(interface), SPI4000_WRITE_DATA0, 4, 1, data);

status = cvmx_twsi_read8(SPI4000_TWSI_ID(interface), SPI4000_DO_WRITE);
    while ((status == 5) || (status == 0xff))
        status = cvmx_twsi_read8(SPI4000_TWSI_ID(interface), SPI4000_GET_WRITE_STATUS);

if (status != 4)
        cvmx_dprintf("SPI4000: write failed with status=0x%x\n", status);
}

/**
 * @INTERNAL
 * Read data from the SPI4000.
 *
 * @param interface Interface the SPI4000 is on. (0 or 1)
 * @param address   Address to read from
 *
 * @return Value at the specified address
 */
static uint32_t __cvmx_spi4000_read(int interface, int address)
{
    int status;
    uint64_t data;

cvmx_twsix_write_ia(0, SPI4000_TWSI_ID(interface), SPI4000_READ_ADDRESS_HIGH, 2, 1, address);

status = cvmx_twsi_read8(SPI4000_TWSI_ID(interface), SPI4000_DO_READ);
    while ((status == 1) || (status == 0xff))
        status = cvmx_twsi_read8(SPI4000_TWSI_ID(interface), SPI4000_GET_READ_STATUS);

if (status)
    {
        cvmx_dprintf("SPI4000: read failed with %d\n", status);
        return 0;
    }

status = cvmx_twsix_read_ia(0, SPI4000_TWSI_ID(interface), SPI4000_READ_DATA0, 4, 1, &data);
    if (status != 4)
    {
        cvmx_dprintf("SPI4000: read failed with %d\n", status);
        return 0;
    }

return data;
}

/**
 * @INTERNAL
 * Write to a PHY using MDIO on the SPI4000
 *
 * @param interface Interface the SPI4000 is on. (0 or 1)
 * @param port      SPI4000 RGMII port to write to. (0-9)
 * @param location  MDIO register to write
 * @param val       Value to write
 */
static void __cvmx_spi4000_mdio_write(int interface, int port, int location, int val)
{
    static int last_value=-1;
    mdio_single_command_t mdio;

mdio.u32 = 0;
    mdio.s.mdi_command = 1;
    mdio.s.op_code = 1;
    mdio.s.phy_address = port;
    mdio.s.reg_address = location;

/* Since the TWSI accesses are very slow, don't update the write value
        if it is the same as the last value */
    if (val != last_value)
    {
        last_value = val;
        __cvmx_spi4000_write(interface, 0x0681, val);
    }

__cvmx_spi4000_write(interface, 0x0680, mdio.u32);
}

/**
 * @INTERNAL
 * Read from a PHY using MDIO on the SPI4000
 *
 * @param interface Interface the SPI4000 is on. (0 or 1)
 * @param port      SPI4000 RGMII port to read from. (0-9)
 * @param location  MDIO register to read
 * @return The MDI read result
 */
static int __cvmx_spi4000_mdio_read(int interface, int port, int location)
{
    mdio_single_command_t mdio;

mdio.u32 = 0;
    mdio.s.mdi_command = 1;
    mdio.s.op_code = 2;
    mdio.s.phy_address = port;
    mdio.s.reg_address = location;
    __cvmx_spi4000_write(interface, 0x0680, mdio.u32);

do
    {
        mdio.u32 = __cvmx_spi4000_read(interface, 0x0680);
    } while (mdio.s.mdi_command);

return __cvmx_spi4000_read(interface, 0x0681) >> 16;
}

/**
 * @INTERNAL
 * Configure the SPI4000 MACs
 */
static void __cvmx_spi4000_configure_mac(int interface)
{
    int port;
    // IXF1010 configuration
    // ---------------------
    //
    // Step 1: Apply soft reset to TxFIFO and MAC
    //         MAC soft reset register. address=0x505
    //         TxFIFO soft reset. address=0x620
    __cvmx_spi4000_write(interface, 0x0505, 0x3ff);  // reset all the MACs
    __cvmx_spi4000_write(interface, 0x0620, 0x3ff);  // reset the TX FIFOs

//         Global address and Configuration Register. address=0x500
    //
    // Step 2: Apply soft reset to RxFIFO and SPI.
    __cvmx_spi4000_write(interface, 0x059e, 0x3ff);  // reset the RX FIFOs

// Step 3a: Take the MAC out of softreset
    //          MAC soft reset register. address=0x505
    __cvmx_spi4000_write(interface, 0x0505, 0x0);    // reset all the MACs

// Step 3b: De-assert port enables.
    //          Global address and Configuration Register. address=0x500
    __cvmx_spi4000_write(interface, 0x0500, 0x0);    // disable all ports

// Step 4: Assert Clock mode change En.
    //         Clock and interface mode Change En. address=Serdes base + 0x14
    //         Serdes (Serializer/de-serializer). address=0x780
    //         [Can't find this one]

for (port=0; port < 10; port++)
    {
        int port_offset = port << 7;

// Step 5: Set MAC interface mode GMII speed.
        //         MAC interface mode and RGMII speed register.
        //             address=port_index+0x10
        //
        //         OUT port_index+0x10, 0x07     //RGMII 1000 Mbps operation.
        __cvmx_spi4000_write(interface, port_offset | 0x0010, 0x3);

// Set the max packet size to 16383 bytes, including the CRC
        __cvmx_spi4000_write(interface, port_offset | 0x000f, 0x3fff);

// Step 6: Change Interface to Copper mode
        //         Interface mode register. address=0x501
        //         [Can't find this]

// Step 7: MAC configuration
        //         Station address configuration.
        //         Source MAC address low register. Source MAC address 31-0.
        //             address=port_index+0x00
        //         Source MAC address high register. Source MAC address 47-32.
        //             address=port_index+0x01
        //         where Port index is 0x0 to 0x5.
        //         This address is inserted in the source address filed when
        //         transmitting pause frames, and is also used to compare against
        //         unicast pause frames at the receiving side.
        //
        //         OUT port_index+0x00, source MAC address low.
        __cvmx_spi4000_write(interface, port_offset | 0x0000, 0x0000);
        //         OUT port_index+0x01, source MAC address high.
        __cvmx_spi4000_write(interface, port_offset | 0x0001, 0x0000);

// Step 8: Set desired duplex mode
        //         Desired duplex register. address=port_index+0x02
        //         [Reserved]

// Step 9: Other configuration.
        //         FC Enable Register.             address=port_index+0x12
        //         Discard Unknown Control Frame.  address=port_index+0x15
        //         Diverse config write register.  address=port_index+0x18
        //         RX Packet Filter register.      address=port_index+0x19
        //
        // Step 9a: Tx FD FC Enabled / Rx FD FC Enabled
        if (CVMX_HELPER_DISABLE_SPI4000_BACKPRESSURE)
            __cvmx_spi4000_write(interface, port_offset | 0x0012, 0);
        else
            __cvmx_spi4000_write(interface, port_offset | 0x0012, 0x7);

// Step 9b: Discard unknown control frames
        __cvmx_spi4000_write(interface, port_offset | 0x0015, 0x1);

// Step 9c: Enable auto-CRC and auto-padding
        __cvmx_spi4000_write(interface, port_offset | 0x0018, 0x11cd); //??

// Step 9d: Drop bad CRC / Drop Pause / No DAF
        __cvmx_spi4000_write(interface, port_offset | 0x0019, 0x00);
    }

// Step 9d: Drop frames
    __cvmx_spi4000_write(interface, 0x059f, 0x03ff);

for (port=0; port < 10; port++)
    {
        // Step 9e: Set the TX FIFO marks
        __cvmx_spi4000_write(interface, port + 0x0600, 0x0900); // TXFIFO High watermark
        __cvmx_spi4000_write(interface, port + 0x060a, 0x0800); // TXFIFO Low watermark
        __cvmx_spi4000_write(interface, port + 0x0614, 0x0380); // TXFIFO threshold
    }

// Step 12: De-assert RxFIFO and SPI Rx/Tx reset
    __cvmx_spi4000_write(interface, 0x059e, 0x0);    // reset the RX FIFOs

// Step 13: De-assert TxFIFO and MAC reset
    __cvmx_spi4000_write(interface, 0x0620, 0x0);    // reset the TX FIFOs

// Step 14: Assert port enable
    //          Global address and Configuration Register. address=0x500
    __cvmx_spi4000_write(interface, 0x0500, 0x03ff); // enable all ports

// Step 15: Disable loopback
    //          [Can't find this one]
}

/**
 * @INTERNAL
 * Configure the SPI4000 PHYs
 */
static void __cvmx_spi4000_configure_phy(int interface)
{
    int port;

/* We use separate loops below since it allows us to save a write
        to the SPI4000 for each repeated value. This adds up to a couple
        of seconds */

/* Update the link state before resets. It takes a while for the links to
        come back after the resets. Most likely they'll come back the same as
        they are now */
    for (port=0; port < 10; port++)
        cvmx_spi4000_check_speed(interface, port);
    /* Enable RGMII DELAYS for TX_CLK and RX_CLK (see spec) */
    for (port=0; port < 10; port++)
        __cvmx_spi4000_mdio_write(interface, port, 0x14, 0x00e2);
    /* Advertise pause and 100 Full Duplex. Don't advertise half duplex or 10Mbpa */
    for (port=0; port < 10; port++)
        __cvmx_spi4000_mdio_write(interface, port, 0x4, 0x0d01);
    /* Enable PHY reset */
    for (port=0; port < 10; port++)
        __cvmx_spi4000_mdio_write(interface, port, 0x0, 0x9140);
}

/**
 * Poll all the SPI4000 port and check its speed
 *
 * @param interface Interface the SPI4000 is on
 * @param port      Port to poll (0-9)
 * @return Status of the port. 0=down. All other values the port is up.
 */
cvmx_gmxx_rxx_rx_inbnd_t cvmx_spi4000_check_speed(int interface, int port)
{
    static int phy_status[10] = {0,};
    cvmx_gmxx_rxx_rx_inbnd_t link;
    int read_status;

link.u64 = 0;

if (!interface_is_spi4000[interface])
        return link;
    if (port>=10)
        return link;

/* Register 0x11: PHY Specific Status Register
         Register   Function         Setting                     Mode   HW Rst SW Rst Notes
                                                                 RO     00     Retain note
         17.15:14   Speed            11 = Reserved
                                                                                      17.a
                                     10 = 1000 Mbps
                                     01 = 100 Mbps
                                     00 = 10 Mbps
         17.13      Duplex           1 = Full-duplex             RO     0      Retain note
                                     0 = Half-duplex                                  17.a
         17.12      Page Received    1 = Page received           RO, LH 0      0
                                     0 = Page not received
                                     1 = Resolved                RO     0      0      note
         17.11      Speed and
                                     0 = Not resolved                                 17.a
                    Duplex
                    Resolved
         17.10      Link (real time) 1 = Link up                 RO     0      0
                                     0 = Link down
                                                                 RO     000    000    note
                                     000 = < 50m
         17.9:7     Cable Length
                                     001 = 50 - 80m                                   17.b
                    (100/1000
                                     010 = 80 - 110m
                    modes only)
                                     011 = 110 - 140m
                                     100 = >140m
         17.6       MDI Crossover    1 = MDIX                    RO     0      0      note
                    Status           0 = MDI                                          17.a
         17.5       Downshift Sta-   1 = Downshift               RO     0      0
                    tus              0 = No Downshift
         17.4       Energy Detect    1 = Sleep                   RO     0      0
                    Status           0 = Active
         17.3       Transmit Pause   1 = Transmit pause enabled  RO     0      0      note17.
                    Enabled          0 = Transmit pause disabled                      a, 17.c
         17.2       Receive Pause    1 = Receive pause enabled   RO     0      0      note17.
                    Enabled          0 = Receive pause disabled                       a, 17.c
         17.1       Polarity (real   1 = Reversed                RO     0      0
                    time)            0 = Normal
         17.0       Jabber (real     1 = Jabber                  RO     0      Retain
                    time)            0 = No jabber
    */
    read_status = __cvmx_spi4000_mdio_read(interface, port, 0x11);
    if ((read_status & (1<<10)) == 0)
        read_status = 0; /* If the link is down, force zero */
    else
        read_status &= 0xe400; /* Strip off all the don't care bits */
    if (read_status != phy_status[port])
    {
        phy_status[port] = read_status;
        if (read_status & (1<<10))
        {
            /* If the link is up, we need to set the speed based on the PHY status */
            if (read_status & (1<<15))
                __cvmx_spi4000_write(interface, (port<<7) | 0x0010, 0x3); /* 1Gbps */
            else
                __cvmx_spi4000_write(interface, (port<<7) | 0x0010, 0x1); /* 100Mbps */
        }
        else
        {
            /* If the link is down, force 1Gbps so TX traffic dumps fast */
            __cvmx_spi4000_write(interface, (port<<7) | 0x0010, 0x3); /* 1Gbps */
        }
    }

if (read_status & (1<<10))
    {
        link.s.status = 1; /* Link up */
        if (read_status & (1<<15))
            link.s.speed = 2;
        else
            link.s.speed = 1;
    }
    else
    {
        link.s.speed = 2; /* Use 1Gbps when down */
        link.s.status = 0; /* Link Down */
    }
    link.s.duplex = ((read_status & (1<<13)) != 0);

return link;
}
#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
EXPORT_SYMBOL(cvmx_spi4000_check_speed);
#endif

/**
 * Return non-zero if the SPI interface has a SPI4000 attached
 *
 * @param interface SPI interface the SPI4000 is connected to
 *
 * @return
 */
int cvmx_spi4000_is_present(int interface)
{
    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
        return 0;
    // Check for the presence of a SPI4000. If it isn't there,
    // these writes will timeout.
    if (cvmx_twsi_write8(SPI4000_TWSI_ID(interface), SPI4000_WRITE_ADDRESS_HIGH, 0))
        return 0;
    if (cvmx_twsi_write8(SPI4000_TWSI_ID(interface), SPI4000_WRITE_ADDRESS_LOW, 0))
        return 0;
    interface_is_spi4000[interface] = 1;
    return 1;
}

/**
 * Initialize the SPI4000 for use
 *
 * @param interface SPI interface the SPI4000 is connected to
 */
int cvmx_spi4000_initialize(int interface)
{
    if (!cvmx_spi4000_is_present(interface))
        return -1;

__cvmx_spi4000_configure_mac(interface);
    __cvmx_spi4000_configure_phy(interface);
    return 0;
}

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