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_align.h
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_bus.h
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_inttypes.h
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_limits.h
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_stdint.h
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_types.h
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asm.h
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atomic.h
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bus.h
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bus_dma.h
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bus_dma_impl.h
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clock.h
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counter.h
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cpu.h
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cpufunc.h
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db_machdep.h
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dump.h
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efi.h
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elf.h
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encoding.h
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endian.h
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exec.h
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float.h
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floatingpoint.h
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fpe.h
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frame.h
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ieeefp.h
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in_cksum.h
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intr.h
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kdb.h
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machdep.h
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md_var.h
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memdev.h
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metadata.h
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minidump.h
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ofw_machdep.h
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param.h
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pcb.h
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pcpu.h
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pcpu_aux.h
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pmap.h
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pmc_mdep.h
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proc.h
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procctl.h
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profile.h
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psl.h
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pte.h
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ptrace.h
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reg.h
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reloc.h
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resource.h
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riscvreg.h
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runq.h
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sbi.h
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setjmp.h
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sf_buf.h
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sigframe.h
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signal.h
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smp.h
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stack.h
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stdarg.h
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sysarch.h
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trap.h
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ucontext.h
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vdso.h
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vm.h
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vmparam.h
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Editing: db_machdep.h
/*- * Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com> * All rights reserved. * * Portions of this software were developed by SRI International and the * University of Cambridge Computer Laboratory under DARPA/AFRL contract * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. * * Portions of this software were developed by the University of Cambridge * Computer Laboratory as part of the CTSRD Project, with support from the * UK Higher Education Innovation Fund (HEIF). * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _MACHINE_DB_MACHDEP_H_ #define _MACHINE_DB_MACHDEP_H_ #include <machine/riscvreg.h> #include <machine/frame.h> #include <machine/trap.h> #define T_BREAKPOINT (SCAUSE_BREAKPOINT) #define T_WATCHPOINT (0) typedef vm_offset_t db_addr_t; typedef long db_expr_t; #define PC_REGS() ((db_addr_t)kdb_frame->tf_sepc) #define BKPT_INST (0x00100073) #define BKPT_SIZE (INSN_SIZE) #define BKPT_SET(inst) (BKPT_INST) #define BKPT_SKIP do { \ uint32_t _instr; \ \ _instr = db_get_value(PC_REGS(), sizeof(uint32_t), FALSE); \ if ((_instr & 0x3) == 0x3) \ kdb_frame->tf_sepc += 4; /* ebreak */ \ else \ kdb_frame->tf_sepc += 2; /* c.ebreak */ \ } while (0) #define db_clear_single_step kdb_cpu_clear_singlestep #define db_set_single_step kdb_cpu_set_singlestep #define IS_BREAKPOINT_TRAP(type, code) (type == T_BREAKPOINT) #define IS_WATCHPOINT_TRAP(type, code) (type == T_WATCHPOINT) #define inst_trap_return(ins) (ins == 0x10000073) /* eret */ #define inst_return(ins) (ins == 0x00008067) /* ret */ #define inst_call(ins) (((ins) & 0x7f) == 111 || \ ((ins) & 0x7f) == 103) /* jal, jalr */ #define inst_load(ins) ({ \ uint32_t tmp_instr = db_get_value(PC_REGS(), sizeof(uint32_t), FALSE); \ is_load_instr(tmp_instr); \ }) #define inst_store(ins) ({ \ uint32_t tmp_instr = db_get_value(PC_REGS(), sizeof(uint32_t), FALSE); \ is_store_instr(tmp_instr); \ }) #define is_load_instr(ins) (((ins) & 0x7f) == 3) #define is_store_instr(ins) (((ins) & 0x7f) == 35) #define next_instr_address(pc, bd) ((bd) ? (pc) : ((pc) + 4)) #define DB_ELFSIZE 64 #endif /* !_MACHINE_DB_MACHDEP_H_ */
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