003 File Manager
Current Path:
/usr/src/sys/contrib/device-tree/Bindings/clock/ti
usr
/
src
/
sys
/
contrib
/
device-tree
/
Bindings
/
clock
/
ti
/
📁
..
📄
adpll.txt
(1.4 KB)
📄
apll.txt
(1.78 KB)
📄
autoidle.txt
(1.2 KB)
📄
clockdomain.txt
(880 B)
📄
composite.txt
(1.59 KB)
📁
davinci
📄
divider.txt
(3.68 KB)
📄
dpll.txt
(2.86 KB)
📄
dra7-atl.txt
(2.81 KB)
📄
fapll.txt
(1.04 KB)
📄
fixed-factor-clock.txt
(1.27 KB)
📄
gate.txt
(3.26 KB)
📄
interface.txt
(1.96 KB)
📄
mux.txt
(2.58 KB)
Editing: dpll.txt
Binding for Texas Instruments DPLL clock. Binding status: Unstable - ABI compatibility may be broken in the future This binding uses the common clock binding[1]. It assumes a register-mapped DPLL with usually two selectable input clocks (reference clock and bypass clock), with digital phase locked loop logic for multiplying the input clock to a desired output clock. This clock also typically supports different operation modes (locked, low power stop etc.) This binding has several sub-types, which effectively result in slightly different setup for the actual DPLL clock. [1] Documentation/devicetree/bindings/clock/clock-bindings.txt Required properties: - compatible : shall be one of: "ti,omap3-dpll-clock", "ti,omap3-dpll-core-clock", "ti,omap3-dpll-per-clock", "ti,omap3-dpll-per-j-type-clock", "ti,omap4-dpll-clock", "ti,omap4-dpll-x2-clock", "ti,omap4-dpll-core-clock", "ti,omap4-dpll-m4xen-clock", "ti,omap4-dpll-j-type-clock", "ti,omap5-mpu-dpll-clock", "ti,am3-dpll-no-gate-clock", "ti,am3-dpll-j-type-clock", "ti,am3-dpll-no-gate-j-type-clock", "ti,am3-dpll-clock", "ti,am3-dpll-core-clock", "ti,am3-dpll-x2-clock", "ti,omap2-dpll-core-clock", - #clock-cells : from common clock binding; shall be set to 0. - clocks : link phandles of parent clocks, first entry lists reference clock and second entry bypass clock - reg : offsets for the register set for controlling the DPLL. Registers are listed in following order: "control" - contains the control register base address "idlest" - contains the idle status register base address "mult-div1" - contains the multiplier / divider register base address "autoidle" - contains the autoidle register base address (optional) ti,am3-* dpll types do not have autoidle register ti,omap2-* dpll type does not support idlest / autoidle registers Optional properties: - DPLL mode setting - defining any one or more of the following overrides default setting. - ti,low-power-stop : DPLL supports low power stop mode, gating output - ti,low-power-bypass : DPLL output matches rate of parent bypass clock - ti,lock : DPLL locks in programmed rate Examples: dpll_core_ck: dpll_core_ck@44e00490 { #clock-cells = <0>; compatible = "ti,omap4-dpll-core-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x490>, <0x45c>, <0x488>, <0x468>; }; dpll2_ck: dpll2_ck@48004004 { #clock-cells = <0>; compatible = "ti,omap3-dpll-clock"; clocks = <&sys_ck>, <&dpll2_fck>; ti,low-power-stop; ti,low-power-bypass; ti,lock; reg = <0x4>, <0x24>, <0x34>, <0x40>; }; dpll_core_ck: dpll_core_ck@44e00490 { #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x90>, <0x5c>, <0x68>; }; dpll_ck: dpll_ck { #clock-cells = <0>; compatible = "ti,omap2-dpll-core-clock"; clocks = <&sys_ck>, <&sys_ck>; reg = <0x0500>, <0x0540>; };
Upload File
Create Folder