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adpll.txt
(1.4 KB)
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apll.txt
(1.78 KB)
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autoidle.txt
(1.2 KB)
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clockdomain.txt
(880 B)
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composite.txt
(1.59 KB)
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davinci
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divider.txt
(3.68 KB)
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dpll.txt
(2.86 KB)
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dra7-atl.txt
(2.81 KB)
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fapll.txt
(1.04 KB)
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fixed-factor-clock.txt
(1.27 KB)
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gate.txt
(3.26 KB)
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interface.txt
(1.96 KB)
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mux.txt
(2.58 KB)
Editing: fapll.txt
Binding for Texas Instruments FAPLL clock. Binding status: Unstable - ABI compatibility may be broken in the future This binding uses the common clock binding[1]. It assumes a register-mapped FAPLL with usually two selectable input clocks (reference clock and bypass clock), and one or more child syntesizers. [1] Documentation/devicetree/bindings/clock/clock-bindings.txt Required properties: - compatible : shall be "ti,dm816-fapll-clock" - #clock-cells : from common clock binding; shall be set to 0. - clocks : link phandles of parent clocks (clk-ref and clk-bypass) - reg : address and length of the register set for controlling the FAPLL. Examples: main_fapll: main_fapll { #clock-cells = <1>; compatible = "ti,dm816-fapll-clock"; reg = <0x400 0x40>; clocks = <&sys_clkin_ck &sys_clkin_ck>; clock-indices = <1>, <2>, <3>, <4>, <5>, <6>, <7>; clock-output-names = "main_pll_clk1", "main_pll_clk2", "main_pll_clk3", "main_pll_clk4", "main_pll_clk5", "main_pll_clk6", "main_pll_clk7"; };
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