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cache.json
(42.66 KB)
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floating-point.json
(3.29 KB)
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frontend.json
(12.45 KB)
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hsw-metrics.json
(20.3 KB)
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memory.json
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other.json
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pipeline.json
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uncore.json
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virtual-memory.json
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Editing: floating-point.json
[ { "PEBS": "1", "PublicDescription": "", "EventCode": "0xC1", "Counter": "0,1,2,3", "UMask": "0x8", "Errata": "HSD56, HSM57", "EventName": "OTHER_ASSISTS.AVX_TO_SSE", "SampleAfterValue": "100003", "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "PEBS": "1", "PublicDescription": "", "EventCode": "0xC1", "Counter": "0,1,2,3", "UMask": "0x10", "Errata": "HSD56, HSM57", "EventName": "OTHER_ASSISTS.SSE_TO_AVX", "SampleAfterValue": "100003", "BriefDescription": "Number of transitions from legacy SSE to AVX-256 when penalty applicable", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.", "EventCode": "0xC6", "Counter": "0,1,2,3", "UMask": "0x7", "EventName": "AVX_INSTS.ALL", "SampleAfterValue": "2000003", "BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "PEBS": "1", "PublicDescription": "", "EventCode": "0xCA", "Counter": "0,1,2,3", "UMask": "0x2", "EventName": "FP_ASSIST.X87_OUTPUT", "SampleAfterValue": "100003", "BriefDescription": "output - Numeric Overflow, Numeric Underflow, Inexact Result", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "PEBS": "1", "PublicDescription": "", "EventCode": "0xCA", "Counter": "0,1,2,3", "UMask": "0x4", "EventName": "FP_ASSIST.X87_INPUT", "SampleAfterValue": "100003", "BriefDescription": "input - Invalid Operation, Denormal Operand, SNaN Operand", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "PEBS": "1", "PublicDescription": "", "EventCode": "0xCA", "Counter": "0,1,2,3", "UMask": "0x8", "EventName": "FP_ASSIST.SIMD_OUTPUT", "SampleAfterValue": "100003", "BriefDescription": "SSE* FP micro-code assist when output value is invalid.", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "PEBS": "1", "PublicDescription": "", "EventCode": "0xCA", "Counter": "0,1,2,3", "UMask": "0x10", "EventName": "FP_ASSIST.SIMD_INPUT", "SampleAfterValue": "100003", "BriefDescription": "Any input SSE* FP Assist", "CounterHTOff": "0,1,2,3,4,5,6,7" }, { "PEBS": "1", "PublicDescription": "", "EventCode": "0xCA", "Counter": "0,1,2,3", "UMask": "0x1e", "EventName": "FP_ASSIST.ANY", "SampleAfterValue": "100003", "BriefDescription": "Counts any FP_ASSIST umask was incrementing", "CounterMask": "1", "CounterHTOff": "0,1,2,3" } ]
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