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fsl,imx7ulp-pm.txt
(871 B)
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fsl,imx7ulp-sim.txt
(638 B)
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fsl,layerscape-dcfg.txt
(664 B)
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fsl,layerscape-scfg.txt
(601 B)
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fsl,scu.txt
(7.59 KB)
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fsl,vf610-mscm-cpucfg.txt
(468 B)
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fsl,vf610-mscm-ir.txt
(1.25 KB)
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m4if.txt
(284 B)
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tigerp.txt
(263 B)
Editing: fsl,vf610-mscm-ir.txt
Freescale Vybrid Miscellaneous System Control - Interrupt Router The MSCM IP contains multiple sub modules, this binding describes the second block of registers which control the interrupt router. The interrupt router allows to configure the recipient of each peripheral interrupt. Furthermore it controls the directed processor interrupts. The module is available in all Vybrid SoC's but is only really useful in dual core configurations (VF6xx which comes with a Cortex-A5/Cortex-M4 combination). Required properties: - compatible: "fsl,vf610-mscm-ir" - reg: the register range of the MSCM Interrupt Router - fsl,cpucfg: The handle to the MSCM CPU configuration node, required to get the current CPU ID - interrupt-controller: Identifies the node as an interrupt controller - #interrupt-cells: Two cells, interrupt number and cells. The hardware interrupt number according to interrupt assignment of the interrupt router is required. Flags get passed only when using GIC as parent. Flags encoding as documented by the GIC bindings. Example: mscm_ir: interrupt-controller@40001800 { compatible = "fsl,vf610-mscm-ir"; reg = <0x40001800 0x400>; fsl,cpucfg = <&mscm_cpucfg>; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; }
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