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📄 fsl-ls1012a-frdm.dts(1.77 KB)
📄 fsl-ls1012a-frwy.dts(619 B)
📄 fsl-ls1012a-oxalis.dts(1.61 KB)
📄 fsl-ls1012a-qds.dts(2.57 KB)
📄 fsl-ls1012a-rdb.dts(771 B)
📄 fsl-ls1012a.dtsi(13.52 KB)
📄 fsl-ls1028a-kontron-kbox-a-230-ls.dts(1.46 KB)
📄 fsl-ls1028a-kontron-sl28-var2.dts(1.34 KB)
📄 fsl-ls1028a-kontron-sl28-var3-ads2.dts(2.16 KB)
📄 fsl-ls1028a-kontron-sl28-var4.dts(1.05 KB)
📄 fsl-ls1028a-kontron-sl28.dts(2.9 KB)
📄 fsl-ls1028a-qds.dts(5.28 KB)
📄 fsl-ls1028a-rdb.dts(4.34 KB)
📄 fsl-ls1028a.dtsi(29.05 KB)
📄 fsl-ls1043-post.dtsi(780 B)
📄 fsl-ls1043a-qds.dts(2.41 KB)
📄 fsl-ls1043a-rdb.dts(3.65 KB)
📄 fsl-ls1043a.dtsi(22.32 KB)
📄 fsl-ls1046-post.dtsi(825 B)
📄 fsl-ls1046a-frwy.dts(2.51 KB)
📄 fsl-ls1046a-qds.dts(2.83 KB)
📄 fsl-ls1046a-rdb.dts(2.83 KB)
📄 fsl-ls1046a.dtsi(22.83 KB)
📄 fsl-ls1088a-qds.dts(2.61 KB)
📄 fsl-ls1088a-rdb.dts(1.82 KB)
📄 fsl-ls1088a.dtsi(22.01 KB)
📄 fsl-ls2080a-qds.dts(512 B)
📄 fsl-ls2080a-rdb.dts(507 B)
📄 fsl-ls2080a-simu.dts(542 B)
📄 fsl-ls2080a.dtsi(3.72 KB)
📄 fsl-ls2088a-qds.dts(458 B)
📄 fsl-ls2088a-rdb.dts(458 B)
📄 fsl-ls2088a.dtsi(3.61 KB)
📄 fsl-ls208xa-qds.dtsi(2.6 KB)
📄 fsl-ls208xa-rdb.dtsi(1.96 KB)
📄 fsl-ls208xa.dtsi(20.25 KB)
📄 fsl-lx2160a-cex7.dtsi(2.39 KB)
📄 fsl-lx2160a-clearfog-cx.dts(315 B)
📄 fsl-lx2160a-clearfog-itx.dtsi(692 B)
📄 fsl-lx2160a-honeycomb.dts(309 B)
📄 fsl-lx2160a-qds.dts(2.45 KB)
📄 fsl-lx2160a-rdb.dts(2.66 KB)
📄 fsl-lx2160a.dtsi(37.57 KB)
📄 imx8mm-beacon-baseboard.dtsi(6.28 KB)
📄 imx8mm-beacon-kit.dts(374 B)
📄 imx8mm-beacon-som.dtsi(9.83 KB)
📄 imx8mm-evk.dts(12.52 KB)
📄 imx8mm-pinfunc.h(63.02 KB)
📄 imx8mm.dtsi(27.25 KB)
📄 imx8mn-ddr4-evk.dts(3.12 KB)
📄 imx8mn-evk.dts(2.54 KB)
📄 imx8mn-evk.dtsi(8.1 KB)
📄 imx8mn-pinfunc.h(64.97 KB)
📄 imx8mn.dtsi(23.93 KB)
📄 imx8mp-evk.dts(6.75 KB)
📄 imx8mp-pinfunc.h(85.33 KB)
📄 imx8mp.dtsi(19.92 KB)
📄 imx8mq-evk.dts(11.98 KB)
📄 imx8mq-hummingboard-pulse.dts(5.94 KB)
📄 imx8mq-librem5-devkit.dts(21.7 KB)
📄 imx8mq-nitrogen.dts(10.51 KB)
📄 imx8mq-phanbell.dts(10.84 KB)
📄 imx8mq-pico-pi.dts(9.96 KB)
📄 imx8mq-pinfunc.h(60.77 KB)
📄 imx8mq-sr-som.dtsi(7.5 KB)
📄 imx8mq-thor96.dts(12.86 KB)
📄 imx8mq-zii-ultra-rmb3.dts(1.72 KB)
📄 imx8mq-zii-ultra-zest.dts(473 B)
📄 imx8mq-zii-ultra.dtsi(16.29 KB)
📄 imx8mq.dtsi(36.02 KB)
📄 imx8qxp-ai_ml.dts(5.86 KB)
📄 imx8qxp-colibri-eval-v3.dts(333 B)
📄 imx8qxp-colibri-eval-v3.dtsi(895 B)
📄 imx8qxp-colibri.dtsi(18.2 KB)
📄 imx8qxp-mek.dts(5.97 KB)
📄 imx8qxp.dtsi(16.6 KB)
📄 qoriq-bman-portals.dtsi(1.87 KB)
📄 qoriq-fman3-0-10g-0.dtsi(845 B)
📄 qoriq-fman3-0-10g-1.dtsi(845 B)
📄 qoriq-fman3-0-1g-0.dtsi(828 B)
📄 qoriq-fman3-0-1g-1.dtsi(828 B)
📄 qoriq-fman3-0-1g-2.dtsi(828 B)
📄 qoriq-fman3-0-1g-3.dtsi(828 B)
📄 qoriq-fman3-0-1g-4.dtsi(828 B)
📄 qoriq-fman3-0-1g-5.dtsi(828 B)
📄 qoriq-fman3-0.dtsi(1.8 KB)
📄 qoriq-qman-portals.dtsi(2.16 KB)
📄 s32v234-evb.dts(371 B)
📄 s32v234.dtsi(3.13 KB)

Editing: fsl-ls2088a.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Freescale Layerscape-2088A family SoC.
 *
 * Copyright 2016 Freescale Semiconductor, Inc.
 * Copyright 2017 NXP
 *
 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
 *
 */

#include "fsl-ls208xa.dtsi"

&cpu {
	cpu0: cpu@0 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x0>;
		clocks = <&clockgen 1 0>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster0_l2>;
		#cooling-cells = <2>;
	};

cpu1: cpu@1 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x1>;
		clocks = <&clockgen 1 0>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster0_l2>;
		#cooling-cells = <2>;
	};

cpu2: cpu@100 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x100>;
		clocks = <&clockgen 1 1>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster1_l2>;
		#cooling-cells = <2>;
	};

cpu3: cpu@101 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x101>;
		clocks = <&clockgen 1 1>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster1_l2>;
		#cooling-cells = <2>;
	};

cpu4: cpu@200 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x200>;
		clocks = <&clockgen 1 2>;
		next-level-cache = <&cluster2_l2>;
		cpu-idle-states = <&CPU_PW20>;
		#cooling-cells = <2>;
	};

cpu5: cpu@201 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x201>;
		clocks = <&clockgen 1 2>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster2_l2>;
		#cooling-cells = <2>;
	};

cpu6: cpu@300 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x300>;
		clocks = <&clockgen 1 3>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster3_l2>;
		#cooling-cells = <2>;
	};

cpu7: cpu@301 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x301>;
		clocks = <&clockgen 1 3>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster3_l2>;
		#cooling-cells = <2>;
	};

cluster0_l2: l2-cache0 {
		compatible = "cache";
	};

cluster1_l2: l2-cache1 {
		compatible = "cache";
	};

cluster2_l2: l2-cache2 {
		compatible = "cache";
	};

cluster3_l2: l2-cache3 {
		compatible = "cache";
	};

CPU_PW20: cpu-pw20 {
		compatible = "arm,idle-state";
		idle-state-name = "PW20";
		arm,psci-suspend-param = <0x0>;
		entry-latency-us = <2000>;
		exit-latency-us = <2000>;
		min-residency-us = <6000>;
	};
};

&pcie1 {
	compatible = "fsl,ls2088a-pcie";
	reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
	       0x20 0x00000000 0x0 0x00002000>; /* configuration space */

ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000
		  0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>;
};

&pcie2 {
	compatible = "fsl,ls2088a-pcie";
	reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
	       0x28 0x00000000 0x0 0x00002000>; /* configuration space */

ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000
		  0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>;
};

&pcie3 {
	compatible = "fsl,ls2088a-pcie";
	reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
	       0x30 0x00000000 0x0 0x00002000>; /* configuration space */

ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000
		  0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>;
};

&pcie4 {
	compatible = "fsl,ls2088a-pcie";
	reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
	       0x38 0x00000000 0x0 0x00002000>; /* configuration space */

ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000
		  0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>;
};

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Editing: fsl-ls2088a.dtsi

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