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dpu.txt
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dsi.txt
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edp.txt
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gmu.yaml
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gpu.txt
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hdmi.txt
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mdp4.txt
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mdp5.txt
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Editing: gmu.yaml
# SPDX-License-Identifier: GPL-2.0-only # Copyright 2019-2020, The Linux Foundation, All Rights Reserved %YAML 1.2 --- $id: "http://devicetree.org/schemas/display/msm/gmu.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: Devicetree bindings for the GMU attached to certain Adreno GPUs maintainers: - Rob Clark <robdclark@gmail.com> description: | These bindings describe the Graphics Management Unit (GMU) that is attached to members of the Adreno A6xx GPU family. The GMU provides on-device power management and support to improve power efficiency and reduce the load on the CPU. properties: compatible: items: - enum: - qcom,adreno-gmu-630.2 - const: qcom,adreno-gmu reg: items: - description: Core GMU registers - description: GMU PDC registers - description: GMU PDC sequence registers reg-names: items: - const: gmu - const: gmu_pdc - const: gmu_pdc_seq clocks: items: - description: GMU clock - description: GPU CX clock - description: GPU AXI clock - description: GPU MEMNOC clock clock-names: items: - const: gmu - const: cxo - const: axi - const: memnoc interrupts: items: - description: GMU HFI interrupt - description: GMU interrupt interrupt-names: items: - const: hfi - const: gmu power-domains: items: - description: CX power domain - description: GX power domain power-domain-names: items: - const: cx - const: gx iommus: maxItems: 1 operating-points-v2: true required: - compatible - reg - reg-names - clocks - clock-names - interrupts - interrupt-names - power-domains - power-domain-names - iommus - operating-points-v2 examples: - | #include <dt-bindings/clock/qcom,gpucc-sdm845.h> #include <dt-bindings/clock/qcom,gcc-sdm845.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> gmu: gmu@506a000 { compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; reg = <0x506a000 0x30000>, <0xb280000 0x10000>, <0xb480000 0x10000>; reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; clocks = <&gpucc GPU_CC_CX_GMU_CLK>, <&gpucc GPU_CC_CXO_CLK>, <&gcc GCC_DDRSS_GPU_AXI_CLK>, <&gcc GCC_GPU_MEMNOC_GFX_CLK>; clock-names = "gmu", "cxo", "axi", "memnoc"; interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hfi", "gmu"; power-domains = <&gpucc GPU_CX_GDSC>, <&gpucc GPU_GX_GDSC>; power-domain-names = "cx", "gx"; iommus = <&adreno_smmu 5>; operating-points-v2 = <&gmu_opp_table>; };
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