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Current Path: /usr/src/sys/contrib/device-tree/src/arm64/hisilicon

usr / src / sys / contrib / device-tree / src / arm64 / hisilicon /

📁 ..
📄 hi3660-coresight.dtsi(8.1 KB)
📄 hi3660-hikey960.dts(14.39 KB)
📄 hi3660.dtsi(31.07 KB)
📄 hi3670-hikey970.dts(9.88 KB)
📄 hi3670.dtsi(18.44 KB)
📄 hi3798cv200-poplar.dts(3.26 KB)
📄 hi3798cv200.dtsi(15.78 KB)
📄 hi6220-coresight.dtsi(8.85 KB)
📄 hi6220-hikey.dts(12.01 KB)
📄 hi6220.dtsi(27.69 KB)
📄 hikey-pinctrl.dtsi(24.59 KB)
📄 hikey960-pinctrl.dtsi(21.32 KB)
📄 hikey970-pinctrl.dtsi(7.58 KB)
📄 hip05-d02.dts(1.39 KB)
📄 hip05.dtsi(7.38 KB)
📄 hip06-d03.dts(626 B)
📄 hip06.dtsi(20.69 KB)
📄 hip07-d05.dts(1.1 KB)
📄 hip07.dtsi(45.45 KB)
📄 poplar-pinctrl.dtsi(2.11 KB)

Editing: hip05-d02.dts

// SPDX-License-Identifier: GPL-2.0-only
/**
 * dts file for Hisilicon D02 Development Board
 *
 * Copyright (C) 2014,2015 Hisilicon Ltd.
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include "hip05.dtsi"

/ {
	model = "Hisilicon Hip05 D02 Development Board";
	compatible = "hisilicon,hip05-d02";

memory@0 {
		device_type = "memory";
		reg = <0x0 0x00000000 0x0 0x80000000>;
	};

aliases {
		serial0 = &uart0;
	};

chosen {
		stdout-path = "serial0:115200n8";
	};

gpio_keys {
		compatible = "gpio-keys";
		#address-cells = <1>;
		#size-cells = <0>;

pwrbutton {
			label = "Power Button";
			gpios = <&porta 8 GPIO_ACTIVE_LOW>;
			linux,code = <116>;
			debounce-interval = <0>;
		};
	};
};

&uart0 {
	status = "ok";
};

&peri_gpio0 {
	status = "ok";
};

&lbc {
	status = "ok";
	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0 0 0x0 0x90000000 0x08000000>,
		 <1 0 0x0 0x98000000 0x08000000>;

nor-flash@0,0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "numonyx,js28f00a", "cfi-flash";
		reg = <0 0x0 0x08000000>;
		bank-width = <2>;
		/* The three parts may not used */
		partition@0 {
			label = "BIOS";
			reg = <0x0 0x300000>;
		};
		partition@300000 {
			label = "Linux";
			reg = <0x300000 0xa00000>;
		};
		partition@1000000 {
			label = "Rootfs";
			reg = <0x01000000 0x02000000>;
		};
	};

cpld@1,0 {
		compatible = "hisilicon,hip05-cpld";
		reg = <1 0x0 0x100>;
	};
};

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Editing: hip05-d02.dts

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