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usr / src / sys / contrib / device-tree / Bindings / reset /

📁 ..
📄 allwinner,sun6i-a31-clock-reset.yaml(1.48 KB)
📄 amlogic,meson-axg-audio-arb.txt(669 B)
📄 amlogic,meson-reset.yaml(985 B)
📄 ath79-reset.txt(580 B)
📄 berlin,reset.txt(490 B)
📄 bitmain,bm1880-reset.txt(515 B)
📄 brcm,bcm63138-pmb.txt(608 B)
📄 brcm,bcm7216-pcie-sata-rescal.yaml(918 B)
📄 brcm,brcmstb-reset.txt(676 B)
📄 fsl,imx-src.txt(1.34 KB)
📄 fsl,imx-src.yaml(1.97 KB)
📄 fsl,imx7-src.txt(1.61 KB)
📄 fsl,imx7-src.yaml(1.34 KB)
📄 hisilicon,hi3660-reset.txt(1.33 KB)
📄 hisilicon,hi6220-reset.txt(1.1 KB)
📄 img,pistachio-reset.txt(1.64 KB)
📄 intel,rcu-gw.yaml(1.61 KB)
📄 lantiq,reset.txt(1.01 KB)
📄 nuvoton,npcm-reset.txt(961 B)
📄 nxp,lpc1850-rgu.txt(1.89 KB)
📄 oxnas,reset.txt(967 B)
📄 qcom,aoss-reset.yaml(1.05 KB)
📄 qcom,pdc-global.yaml(1.06 KB)
📄 renesas,rst.yaml(2.09 KB)
📄 reset.txt(2.9 KB)
📄 sirf,rstc.txt(1.25 KB)
📄 snps,axs10x-reset.txt(922 B)
📄 snps,dw-reset.txt(710 B)
📄 snps,hsdk-reset.txt(761 B)
📄 socfpga-reset.txt(488 B)
📄 socionext,uniphier-reset.yaml(3.05 KB)
📄 st,sti-picophyreset.txt(1.44 KB)
📄 st,sti-powerdown.txt(1.48 KB)
📄 st,sti-softreset.txt(1.37 KB)
📄 st,stm32-rcc.txt(227 B)
📄 st,stm32mp1-rcc.txt(237 B)
📄 ti,sci-reset.txt(2.24 KB)
📄 ti-syscon-reset.txt(3.11 KB)
📄 uniphier-reset.txt(1.86 KB)
📄 xlnx,zynqmp-reset.txt(1.25 KB)
📄 zte,zx2967-reset.txt(502 B)
📄 zynq-reset.txt(1.35 KB)

Editing: hisilicon,hi3660-reset.txt

Hisilicon System Reset Controller
======================================

Please also refer to reset.txt in this directory for common reset
controller binding usage.

The reset controller registers are part of the system-ctl block on
hi3660 and hi3670 SoCs.

Required properties:
- compatible: should be one of the following:
		 "hisilicon,hi3660-reset" for HI3660
		 "hisilicon,hi3670-reset", "hisilicon,hi3660-reset" for HI3670
- hisi,rst-syscon: phandle of the reset's syscon.
- #reset-cells : Specifies the number of cells needed to encode a
  reset source.  The type shall be a <u32> and the value shall be 2.

Cell #1 : offset of the reset assert control
	           register from the syscon register base
		   offset + 4: deassert control register
		   offset + 8: status control register
	 Cell #2 : bit position of the reset in the reset control register

Example:
	iomcu: iomcu@ffd7e000 {
		compatible = "hisilicon,hi3660-iomcu", "syscon";
		reg = <0x0 0xffd7e000 0x0 0x1000>;
	};

iomcu_rst: iomcu_rst_controller {
		compatible = "hisilicon,hi3660-reset";
		hisi,rst-syscon = <&iomcu>;
		#reset-cells = <2>;
	};

Specifying reset lines connected to IP modules
==============================================
example:

i2c0: i2c@..... {
                ...
		resets = <&iomcu_rst 0x20 3>; /* offset: 0x20; bit: 3 */
                ...
        };

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Editing: hisilicon,hi3660-reset.txt

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