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usr / src / sys / contrib / device-tree / src / arm64 / freescale /

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📄 fsl-ls1012a-frdm.dts(1.77 KB)
📄 fsl-ls1012a-frwy.dts(619 B)
📄 fsl-ls1012a-oxalis.dts(1.61 KB)
📄 fsl-ls1012a-qds.dts(2.57 KB)
📄 fsl-ls1012a-rdb.dts(771 B)
📄 fsl-ls1012a.dtsi(13.52 KB)
📄 fsl-ls1028a-kontron-kbox-a-230-ls.dts(1.46 KB)
📄 fsl-ls1028a-kontron-sl28-var2.dts(1.34 KB)
📄 fsl-ls1028a-kontron-sl28-var3-ads2.dts(2.16 KB)
📄 fsl-ls1028a-kontron-sl28-var4.dts(1.05 KB)
📄 fsl-ls1028a-kontron-sl28.dts(2.9 KB)
📄 fsl-ls1028a-qds.dts(5.28 KB)
📄 fsl-ls1028a-rdb.dts(4.34 KB)
📄 fsl-ls1028a.dtsi(29.05 KB)
📄 fsl-ls1043-post.dtsi(780 B)
📄 fsl-ls1043a-qds.dts(2.41 KB)
📄 fsl-ls1043a-rdb.dts(3.65 KB)
📄 fsl-ls1043a.dtsi(22.32 KB)
📄 fsl-ls1046-post.dtsi(825 B)
📄 fsl-ls1046a-frwy.dts(2.51 KB)
📄 fsl-ls1046a-qds.dts(2.83 KB)
📄 fsl-ls1046a-rdb.dts(2.83 KB)
📄 fsl-ls1046a.dtsi(22.83 KB)
📄 fsl-ls1088a-qds.dts(2.61 KB)
📄 fsl-ls1088a-rdb.dts(1.82 KB)
📄 fsl-ls1088a.dtsi(22.01 KB)
📄 fsl-ls2080a-qds.dts(512 B)
📄 fsl-ls2080a-rdb.dts(507 B)
📄 fsl-ls2080a-simu.dts(542 B)
📄 fsl-ls2080a.dtsi(3.72 KB)
📄 fsl-ls2088a-qds.dts(458 B)
📄 fsl-ls2088a-rdb.dts(458 B)
📄 fsl-ls2088a.dtsi(3.61 KB)
📄 fsl-ls208xa-qds.dtsi(2.6 KB)
📄 fsl-ls208xa-rdb.dtsi(1.96 KB)
📄 fsl-ls208xa.dtsi(20.25 KB)
📄 fsl-lx2160a-cex7.dtsi(2.39 KB)
📄 fsl-lx2160a-clearfog-cx.dts(315 B)
📄 fsl-lx2160a-clearfog-itx.dtsi(692 B)
📄 fsl-lx2160a-honeycomb.dts(309 B)
📄 fsl-lx2160a-qds.dts(2.45 KB)
📄 fsl-lx2160a-rdb.dts(2.66 KB)
📄 fsl-lx2160a.dtsi(37.57 KB)
📄 imx8mm-beacon-baseboard.dtsi(6.28 KB)
📄 imx8mm-beacon-kit.dts(374 B)
📄 imx8mm-beacon-som.dtsi(9.83 KB)
📄 imx8mm-evk.dts(12.52 KB)
📄 imx8mm-pinfunc.h(63.02 KB)
📄 imx8mm.dtsi(27.25 KB)
📄 imx8mn-ddr4-evk.dts(3.12 KB)
📄 imx8mn-evk.dts(2.54 KB)
📄 imx8mn-evk.dtsi(8.1 KB)
📄 imx8mn-pinfunc.h(64.97 KB)
📄 imx8mn.dtsi(23.93 KB)
📄 imx8mp-evk.dts(6.75 KB)
📄 imx8mp-pinfunc.h(85.33 KB)
📄 imx8mp.dtsi(19.92 KB)
📄 imx8mq-evk.dts(11.98 KB)
📄 imx8mq-hummingboard-pulse.dts(5.94 KB)
📄 imx8mq-librem5-devkit.dts(21.7 KB)
📄 imx8mq-nitrogen.dts(10.51 KB)
📄 imx8mq-phanbell.dts(10.84 KB)
📄 imx8mq-pico-pi.dts(9.96 KB)
📄 imx8mq-pinfunc.h(60.77 KB)
📄 imx8mq-sr-som.dtsi(7.5 KB)
📄 imx8mq-thor96.dts(12.86 KB)
📄 imx8mq-zii-ultra-rmb3.dts(1.72 KB)
📄 imx8mq-zii-ultra-zest.dts(473 B)
📄 imx8mq-zii-ultra.dtsi(16.29 KB)
📄 imx8mq.dtsi(36.02 KB)
📄 imx8qxp-ai_ml.dts(5.86 KB)
📄 imx8qxp-colibri-eval-v3.dts(333 B)
📄 imx8qxp-colibri-eval-v3.dtsi(895 B)
📄 imx8qxp-colibri.dtsi(18.2 KB)
📄 imx8qxp-mek.dts(5.97 KB)
📄 imx8qxp.dtsi(16.6 KB)
📄 qoriq-bman-portals.dtsi(1.87 KB)
📄 qoriq-fman3-0-10g-0.dtsi(845 B)
📄 qoriq-fman3-0-10g-1.dtsi(845 B)
📄 qoriq-fman3-0-1g-0.dtsi(828 B)
📄 qoriq-fman3-0-1g-1.dtsi(828 B)
📄 qoriq-fman3-0-1g-2.dtsi(828 B)
📄 qoriq-fman3-0-1g-3.dtsi(828 B)
📄 qoriq-fman3-0-1g-4.dtsi(828 B)
📄 qoriq-fman3-0-1g-5.dtsi(828 B)
📄 qoriq-fman3-0.dtsi(1.8 KB)
📄 qoriq-qman-portals.dtsi(2.16 KB)
📄 s32v234-evb.dts(371 B)
📄 s32v234.dtsi(3.13 KB)

Editing: imx8mp-evk.dts

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019 NXP
 */

/dts-v1/;

#include "imx8mp.dtsi"

/ {
	model = "NXP i.MX8MPlus EVK board";
	compatible = "fsl,imx8mp-evk", "fsl,imx8mp";

chosen {
		stdout-path = &uart2;
	};

gpio-leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_led>;

status {
			label = "yellow:status";
			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};
	};

memory@40000000 {
		device_type = "memory";
		reg = <0x0 0x40000000 0 0xc0000000>,
		      <0x1 0x00000000 0 0xc0000000>;
	};

reg_usdhc2_vmmc: regulator-usdhc2 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy1>;
	fsl,magic-packet;
	status = "okay";

mdio {
		#address-cells = <1>;
		#size-cells = <0>;

ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			eee-broken-1000t;
			reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
		};
	};
};

&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

pca6416: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&snvs_pwrkey {
	status = "okay";
};

&uart2 {
	/* console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&usdhc2 {
	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	bus-width = <4>;
	status = "okay";
};

&usdhc3 {
	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";

pinctrl_fec: fecgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x19
		>;
	};

pinctrl_gpio_led: gpioledgrp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x19
		>;
	};

pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c3
			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c3
		>;
	};

pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x41
		>;
	};

pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x49
			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x49
		>;
	};

pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1
		>;
	};

pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
		>;
	};

pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
		>;
	};

pinctrl_usdhc2_gpio: usdhc2grp-gpio {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x1c4
		>;
	};

pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190
		>;
	};

pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194
		>;
	};

pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
		>;
	};

pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0xc6
		>;
	};
};

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Editing: imx8mp-evk.dts

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