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📄 apq8016-sbc.dts(277 B)
📄 apq8016-sbc.dtsi(18.56 KB)
📄 apq8096-db820c.dts(291 B)
📄 apq8096-db820c.dtsi(24.67 KB)
📄 apq8096-ifc6640.dts(8.73 KB)
📄 ipq6018-cp01-c1.dts(1.06 KB)
📄 ipq6018.dtsi(9.94 KB)
📄 ipq8074-hk01.dts(1.35 KB)
📄 ipq8074.dtsi(16.82 KB)
📄 msm8916-longcheer-l8150.dts(4.54 KB)
📄 msm8916-mtp.dts(307 B)
📄 msm8916-mtp.dtsi(450 B)
📄 msm8916-pins.dtsi(8.97 KB)
📄 msm8916-samsung-a2015-common.dtsi(6.71 KB)
📄 msm8916-samsung-a3u-eur.dts(1.13 KB)
📄 msm8916-samsung-a5u-eur.dts(843 B)
📄 msm8916.dtsi(42.93 KB)
📄 msm8992-bullhead-rev-101.dts(5.61 KB)
📄 msm8992-msft-lumia-talkman.dts(796 B)
📄 msm8992-pins.dtsi(1.56 KB)
📄 msm8992-xiaomi-libra.dts(7.16 KB)
📄 msm8992.dtsi(13.31 KB)
📄 msm8994-angler-rev-101.dts(706 B)
📄 msm8994-pins.dtsi(542 B)
📄 msm8994-smd-rpm.dtsi(5.97 KB)
📄 msm8994-sony-xperia-kitakami-sumire.dts(226 B)
📄 msm8994-sony-xperia-kitakami.dtsi(4.68 KB)
📄 msm8994.dtsi(15.28 KB)
📄 msm8996-mtp.dts(254 B)
📄 msm8996-mtp.dtsi(291 B)
📄 msm8996-pins.dtsi(10.37 KB)
📄 msm8996.dtsi(53.71 KB)
📄 msm8998-asus-novago-tp370ql.dts(811 B)
📄 msm8998-clamshell.dtsi(7.74 KB)
📄 msm8998-hp-envy-x2.dts(532 B)
📄 msm8998-lenovo-miix-630.dts(657 B)
📄 msm8998-mtp.dts(267 B)
📄 msm8998-mtp.dtsi(8.4 KB)
📄 msm8998-pins.dtsi(1.85 KB)
📄 msm8998.dtsi(44.87 KB)
📄 pm6150.dtsi(1.71 KB)
📄 pm6150l.dtsi(750 B)
📄 pm660.dtsi(1012 B)
📄 pm660l.dtsi(746 B)
📄 pm8004.dtsi(564 B)
📄 pm8005.dtsi(715 B)
📄 pm8009.dtsi(741 B)
📄 pm8150.dtsi(2.42 KB)
📄 pm8150b.dtsi(2.14 KB)
📄 pm8150l.dtsi(2.04 KB)
📄 pm8916.dtsi(3.88 KB)
📄 pm8994.dtsi(2.28 KB)
📄 pm8998.dtsi(2.37 KB)
📄 pmi8994.dtsi(787 B)
📄 pmi8998.dtsi(885 B)
📄 pms405.dtsi(3.13 KB)
📄 qcs404-evb-1000.dts(256 B)
📄 qcs404-evb-4000.dts(1.71 KB)
📄 qcs404-evb.dtsi(6.75 KB)
📄 qcs404.dtsi(38.84 KB)
📄 sc7180-idp.dts(11.03 KB)
📄 sc7180.dtsi(98.57 KB)
📄 sdm630-sony-xperia-ganges-kirin.dts(220 B)
📄 sdm630-sony-xperia-ganges.dtsi(753 B)
📄 sdm630-sony-xperia-nile-discovery.dts(230 B)
📄 sdm630-sony-xperia-nile-pioneer.dts(222 B)
📄 sdm630-sony-xperia-nile-voyager.dts(337 B)
📄 sdm630-sony-xperia-nile.dtsi(2.53 KB)
📄 sdm630.dtsi(27.11 KB)
📄 sdm636-sony-xperia-ganges-mermaid.dts(542 B)
📄 sdm660-xiaomi-lavender.dts(754 B)
📄 sdm660.dtsi(7.38 KB)
📄 sdm845-cheza-r1.dts(4.64 KB)
📄 sdm845-cheza-r2.dts(4.67 KB)
📄 sdm845-cheza-r3.dts(3.1 KB)
📄 sdm845-cheza.dtsi(25.95 KB)
📄 sdm845-db845c.dts(22.18 KB)
📄 sdm845-mtp.dts(13.04 KB)
📄 sdm845.dtsi(118.59 KB)
📄 sdm850-lenovo-yoga-c630.dts(10.69 KB)
📄 sm8150-mtp.dts(9.72 KB)
📄 sm8150.dtsi(42.98 KB)
📄 sm8250-mtp.dts(10.09 KB)
📄 sm8250.dtsi(47.11 KB)

Editing: ipq8074.dtsi

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-ipq8074.h>

/ {
	model = "Qualcomm Technologies, Inc. IPQ8074";
	compatible = "qcom,ipq8074";

clocks {
		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			clock-frequency = <32000>;
			#clock-cells = <0>;
		};

xo: xo {
			compatible = "fixed-clock";
			clock-frequency = <19200000>;
			#clock-cells = <0>;
		};
	};

cpus {
		#address-cells = <0x1>;
		#size-cells = <0x0>;

CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x1>;
			next-level-cache = <&L2_0>;
		};

CPU2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x2>;
			next-level-cache = <&L2_0>;
		};

CPU3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x3>;
			next-level-cache = <&L2_0>;
		};

L2_0: l2-cache {
			compatible = "cache";
			cache-level = <0x2>;
		};
	};

pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

soc: soc {
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges = <0 0 0 0xffffffff>;
		compatible = "simple-bus";

ssphy_1: phy@58000 {
			compatible = "qcom,ipq8074-qmp-usb3-phy";
			reg = <0x00058000 0x1c4>;
			#clock-cells = <1>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

clocks = <&gcc GCC_USB1_AUX_CLK>,
				<&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
				<&xo>;
			clock-names = "aux", "cfg_ahb", "ref";

resets =  <&gcc GCC_USB1_PHY_BCR>,
				<&gcc GCC_USB3PHY_1_PHY_BCR>;
			reset-names = "phy","common";
			status = "disabled";

usb1_ssphy: lane@58200 {
				reg = <0x00058200 0x130>,       /* Tx */
				      <0x00058400 0x200>,     /* Rx */
				      <0x00058800 0x1f8>,     /* PCS  */
				      <0x00058600 0x044>;     /* PCS misc*/
				#phy-cells = <0>;
				clocks = <&gcc GCC_USB1_PIPE_CLK>;
				clock-names = "pipe0";
				clock-output-names = "gcc_usb1_pipe_clk_src";
			};
		};

qusb_phy_1: phy@59000 {
			compatible = "qcom,ipq8074-qusb2-phy";
			reg = <0x00059000 0x180>;
			#phy-cells = <0>;

clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
				 <&xo>;
			clock-names = "cfg_ahb", "ref";

resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
			status = "disabled";
		};

ssphy_0: phy@78000 {
			compatible = "qcom,ipq8074-qmp-usb3-phy";
			reg = <0x00078000 0x1c4>;
			#clock-cells = <1>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

clocks = <&gcc GCC_USB0_AUX_CLK>,
				<&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
				<&xo>;
			clock-names = "aux", "cfg_ahb", "ref";

resets =  <&gcc GCC_USB0_PHY_BCR>,
				<&gcc GCC_USB3PHY_0_PHY_BCR>;
			reset-names = "phy","common";
			status = "disabled";

usb0_ssphy: lane@78200 {
				reg = <0x00078200 0x130>,       /* Tx */
				      <0x00078400 0x200>,     /* Rx */
				      <0x00078800 0x1f8>,     /* PCS  */
				      <0x00078600 0x044>;     /* PCS misc*/
				#phy-cells = <0>;
				clocks = <&gcc GCC_USB0_PIPE_CLK>;
				clock-names = "pipe0";
				clock-output-names = "gcc_usb0_pipe_clk_src";
			};
		};

qusb_phy_0: phy@79000 {
			compatible = "qcom,ipq8074-qusb2-phy";
			reg = <0x00079000 0x180>;
			#phy-cells = <0>;

clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
				 <&xo>;
			clock-names = "cfg_ahb", "ref";

resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
		};

pcie_phy0: phy@86000 {
			compatible = "qcom,ipq8074-qmp-pcie-phy";
			reg = <0x00086000 0x1000>;
			#phy-cells = <0>;
			clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
			clock-names = "pipe_clk";
			clock-output-names = "pcie20_phy0_pipe_clk";

resets = <&gcc GCC_PCIE0_PHY_BCR>,
				<&gcc GCC_PCIE0PHY_PHY_BCR>;
			reset-names = "phy",
				      "common";
			status = "disabled";
		};

pcie_phy1: phy@8e000 {
			compatible = "qcom,ipq8074-qmp-pcie-phy";
			reg = <0x0008e000 0x1000>;
			#phy-cells = <0>;
			clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
			clock-names = "pipe_clk";
			clock-output-names = "pcie20_phy1_pipe_clk";

resets = <&gcc GCC_PCIE1_PHY_BCR>,
				<&gcc GCC_PCIE1PHY_PHY_BCR>;
			reset-names = "phy",
				      "common";
			status = "disabled";
		};

tlmm: pinctrl@1000000 {
			compatible = "qcom,ipq8074-pinctrl";
			reg = <0x01000000 0x300000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			gpio-ranges = <&tlmm 0 0 70>;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;

serial_4_pins: serial4-pinmux {
				pins = "gpio23", "gpio24";
				function = "blsp4_uart1";
				drive-strength = <8>;
				bias-disable;
			};

i2c_0_pins: i2c-0-pinmux {
				pins = "gpio42", "gpio43";
				function = "blsp1_i2c";
				drive-strength = <8>;
				bias-disable;
			};

spi_0_pins: spi-0-pins {
				pins = "gpio38", "gpio39", "gpio40", "gpio41";
				function = "blsp0_spi";
				drive-strength = <8>;
				bias-disable;
			};

hsuart_pins: hsuart-pins {
				pins = "gpio46", "gpio47", "gpio48", "gpio49";
				function = "blsp2_uart";
				drive-strength = <8>;
				bias-disable;
			};

qpic_pins: qpic-pins {
				pins = "gpio1", "gpio3", "gpio4",
				       "gpio5", "gpio6", "gpio7",
				       "gpio8", "gpio10", "gpio11",
				       "gpio12", "gpio13", "gpio14",
				       "gpio15", "gpio16", "gpio17";
				function = "qpic";
				drive-strength = <8>;
				bias-disable;
			};
		};

gcc: gcc@1800000 {
			compatible = "qcom,gcc-ipq8074";
			reg = <0x01800000 0x80000>;
			#clock-cells = <0x1>;
			#reset-cells = <0x1>;
		};

sdhc_1: sdhci@7824900 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0x7824900 0x500>, <0x7824000 0x800>;
			reg-names = "hc_mem", "core_mem";

interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";

clocks = <&xo>,
				 <&gcc GCC_SDCC1_AHB_CLK>,
				 <&gcc GCC_SDCC1_APPS_CLK>;
			clock-names = "xo", "iface", "core";
			max-frequency = <384000000>;
			mmc-ddr-1_8v;
			mmc-hs200-1_8v;
			mmc-hs400-1_8v;
			bus-width = <8>;

status = "disabled";
		};

blsp_dma: dma@7884000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x07884000 0x2b000>;
			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

blsp1_uart1: serial@78af000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x078af000 0x200>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

blsp1_uart3: serial@78b1000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x078b1000 0x200>;
			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
				<&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 4>,
				<&blsp_dma 5>;
			dma-names = "tx", "rx";
			pinctrl-0 = <&hsuart_pins>;
			pinctrl-names = "default";
			status = "disabled";
		};

blsp1_uart5: serial@78b3000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x078b3000 0x200>;
			interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			pinctrl-0 = <&serial_4_pins>;
			pinctrl-names = "default";
			status = "disabled";
		};

blsp1_spi1: spi@78b5000 {
			compatible = "qcom,spi-qup-v2.2.1";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x078b5000 0x600>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			spi-max-frequency = <50000000>;
			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
				<&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 12>, <&blsp_dma 13>;
			dma-names = "tx", "rx";
			pinctrl-0 = <&spi_0_pins>;
			pinctrl-names = "default";
			status = "disabled";
		};

blsp1_i2c2: i2c@78b6000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x078b6000 0x600>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			clock-frequency = <400000>;
			dmas = <&blsp_dma 15>, <&blsp_dma 14>;
			dma-names = "rx", "tx";
			pinctrl-0 = <&i2c_0_pins>;
			pinctrl-names = "default";
			status = "disabled";
		};

blsp1_i2c3: i2c@78b7000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x078b7000 0x600>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			clock-frequency = <100000>;
			dmas = <&blsp_dma 17>, <&blsp_dma 16>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

qpic_bam: dma@7984000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x07984000 0x1a000>;
			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_QPIC_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
			status = "disabled";
		};

qpic_nand: nand@79b0000 {
			compatible = "qcom,ipq8074-nand";
			reg = <0x079b0000 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&gcc GCC_QPIC_CLK>,
				 <&gcc GCC_QPIC_AHB_CLK>;
			clock-names = "core", "aon";

dmas = <&qpic_bam 0>,
			       <&qpic_bam 1>,
			       <&qpic_bam 2>;
			dma-names = "tx", "rx", "cmd";
			pinctrl-0 = <&qpic_pins>;
			pinctrl-names = "default";
			status = "disabled";
		};

usb_0: usb@8af8800 {
			compatible = "qcom,dwc3";
			reg = <0x08af8800 0x400>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
				<&gcc GCC_USB0_MASTER_CLK>,
				<&gcc GCC_USB0_SLEEP_CLK>,
				<&gcc GCC_USB0_MOCK_UTMI_CLK>;
			clock-names = "sys_noc_axi",
				"master",
				"sleep",
				"mock_utmi";

assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
					  <&gcc GCC_USB0_MASTER_CLK>,
					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
			assigned-clock-rates = <133330000>,
						<133330000>,
						<19200000>;

resets = <&gcc GCC_USB0_BCR>;
			status = "disabled";

dwc_0: dwc3@8a00000 {
				compatible = "snps,dwc3";
				reg = <0x8a00000 0xcd00>;
				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
				phys = <&qusb_phy_0>, <&usb0_ssphy>;
				phy-names = "usb2-phy", "usb3-phy";
				tx-fifo-resize;
				snps,is-utmi-l1-suspend;
				snps,hird-threshold = /bits/ 8 <0x0>;
				snps,dis_u2_susphy_quirk;
				snps,dis_u3_susphy_quirk;
				dr_mode = "host";
			};
		};

usb_1: usb@8cf8800 {
			compatible = "qcom,dwc3";
			reg = <0x08cf8800 0x400>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
				<&gcc GCC_USB1_MASTER_CLK>,
				<&gcc GCC_USB1_SLEEP_CLK>,
				<&gcc GCC_USB1_MOCK_UTMI_CLK>;
			clock-names = "sys_noc_axi",
				"master",
				"sleep",
				"mock_utmi";

assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
					  <&gcc GCC_USB1_MASTER_CLK>,
					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
			assigned-clock-rates = <133330000>,
						<133330000>,
						<19200000>;

resets = <&gcc GCC_USB1_BCR>;
			status = "disabled";

dwc_1: dwc3@8c00000 {
				compatible = "snps,dwc3";
				reg = <0x8c00000 0xcd00>;
				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
				phys = <&qusb_phy_1>, <&usb1_ssphy>;
				phy-names = "usb2-phy", "usb3-phy";
				tx-fifo-resize;
				snps,is-utmi-l1-suspend;
				snps,hird-threshold = /bits/ 8 <0x0>;
				snps,dis_u2_susphy_quirk;
				snps,dis_u3_susphy_quirk;
				dr_mode = "host";
			};
		};

intc: interrupt-controller@b000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <0x3>;
			reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
		};

timer {
			compatible = "arm,armv8-timer";
			interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
				     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
				     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
				     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
		};

timer@b120000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0x0b120000 0x1000>;
			clock-frequency = <19200000>;

frame@b120000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b121000 0x1000>,
				      <0x0b122000 0x1000>;
			};

frame@b123000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b123000 0x1000>;
				status = "disabled";
			};

frame@b124000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b124000 0x1000>;
				status = "disabled";
			};

frame@b125000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b125000 0x1000>;
				status = "disabled";
			};

frame@b126000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b126000 0x1000>;
				status = "disabled";
			};

frame@b127000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b127000 0x1000>;
				status = "disabled";
			};

frame@b128000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b128000 0x1000>;
				status = "disabled";
			};
		};

pcie1: pci@10000000 {
			compatible = "qcom,pcie-ipq8074";
			reg =  <0x10000000 0xf1d
				0x10000f20 0xa8
				0x00088000 0x2000
				0x10100000 0x1000>;
			reg-names = "dbi", "elbi", "parf", "config";
			device_type = "pci";
			linux,pci-domain = <1>;
			bus-range = <0x00 0xff>;
			num-lanes = <1>;
			#address-cells = <3>;
			#size-cells = <2>;

phys = <&pcie_phy1>;
			phy-names = "pciephy";

ranges = <0x81000000 0 0x10200000 0x10200000
				  0 0x100000   /* downstream I/O */
				  0x82000000 0 0x10300000 0x10300000
				  0 0xd00000>; /* non-prefetchable memory */

interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 142
					 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
					<0 0 0 2 &intc 0 143
					 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
					<0 0 0 3 &intc 0 144
					 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
					<0 0 0 4 &intc 0 145
					 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
				 <&gcc GCC_PCIE1_AXI_M_CLK>,
				 <&gcc GCC_PCIE1_AXI_S_CLK>,
				 <&gcc GCC_PCIE1_AHB_CLK>,
				 <&gcc GCC_PCIE1_AUX_CLK>;
			clock-names = "iface",
				      "axi_m",
				      "axi_s",
				      "ahb",
				      "aux";
			resets = <&gcc GCC_PCIE1_PIPE_ARES>,
				 <&gcc GCC_PCIE1_SLEEP_ARES>,
				 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
				 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
				 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
				 <&gcc GCC_PCIE1_AHB_ARES>,
				 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
			reset-names = "pipe",
				      "sleep",
				      "sticky",
				      "axi_m",
				      "axi_s",
				      "ahb",
				      "axi_m_sticky";
			status = "disabled";
		};

pcie0: pci@20000000 {
			compatible = "qcom,pcie-ipq8074";
			reg =  <0x20000000 0xf1d
				0x20000f20 0xa8
				0x00080000 0x2000
				0x20100000 0x1000>;
			reg-names = "dbi", "elbi", "parf", "config";
			device_type = "pci";
			linux,pci-domain = <0>;
			bus-range = <0x00 0xff>;
			num-lanes = <1>;
			#address-cells = <3>;
			#size-cells = <2>;

phys = <&pcie_phy0>;
			phy-names = "pciephy";

ranges = <0x81000000 0 0x20200000 0x20200000
				  0 0x100000   /* downstream I/O */
				  0x82000000 0 0x20300000 0x20300000
				  0 0xd00000>; /* non-prefetchable memory */

interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 75
					 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
					<0 0 0 2 &intc 0 78
					 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
					<0 0 0 3 &intc 0 79
					 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
					<0 0 0 4 &intc 0 83
					 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
				 <&gcc GCC_PCIE0_AXI_M_CLK>,
				 <&gcc GCC_PCIE0_AXI_S_CLK>,
				 <&gcc GCC_PCIE0_AHB_CLK>,
				 <&gcc GCC_PCIE0_AUX_CLK>;

clock-names = "iface",
				      "axi_m",
				      "axi_s",
				      "ahb",
				      "aux";
			resets = <&gcc GCC_PCIE0_PIPE_ARES>,
				 <&gcc GCC_PCIE0_SLEEP_ARES>,
				 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
				 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
				 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
				 <&gcc GCC_PCIE0_AHB_ARES>,
				 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
			reset-names = "pipe",
				      "sleep",
				      "sticky",
				      "axi_m",
				      "axi_s",
				      "ahb",
				      "axi_m_sticky";
			status = "disabled";
		};
	};
};

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