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📄 acphy.c(6.8 KB)
📄 acphyreg.h(3.39 KB)
📄 amphy.c(5.68 KB)
📄 amphyreg.h(3.71 KB)
📄 atphy.c(9.06 KB)
📄 atphyreg.h(2.46 KB)
📄 axphy.c(4.27 KB)
📄 bmtphy.c(7.2 KB)
📄 bmtphyreg.h(7.51 KB)
📄 brgphy.c(32.55 KB)
📄 brgphyreg.h(18.76 KB)
📄 ciphy.c(9.45 KB)
📄 ciphyreg.h(16.78 KB)
📄 e1000phy.c(13.82 KB)
📄 e1000phyreg.h(13.79 KB)
📄 gentbi.c(7.33 KB)
📄 icsphy.c(6.76 KB)
📄 icsphyreg.h(4.99 KB)
📄 ip1000phy.c(8.88 KB)
📄 ip1000phyreg.h(6.73 KB)
📄 jmphy.c(8.38 KB)
📄 jmphyreg.h(4.07 KB)
📄 lxtphy.c(7.35 KB)
📄 lxtphyreg.h(3.64 KB)
📄 micphy.c(9.27 KB)
📄 mii.c(16.35 KB)
📄 mii.h(10.3 KB)
📄 mii_bitbang.c(4.46 KB)
📄 mii_bitbang.h(2.36 KB)
📄 mii_fdt.c(6.02 KB)
📄 mii_fdt.h(2.9 KB)
📄 mii_physubr.c(17.29 KB)
📄 miibus_if.m(533 B)
📄 miidevs(16.37 KB)
📄 miivar.h(9.61 KB)
📄 nsgphy.c(6.74 KB)
📄 nsgphyreg.h(3.43 KB)
📄 nsphy.c(9.02 KB)
📄 nsphyreg.h(4.39 KB)
📄 nsphyter.c(7.77 KB)
📄 nsphyterreg.h(8.3 KB)
📄 pnaphy.c(4.19 KB)
📄 qsphy.c(6.26 KB)
📄 qsphyreg.h(3.74 KB)
📄 rdcphy.c(5.91 KB)
📄 rdcphyreg.h(2.67 KB)
📄 rgephy.c(15.06 KB)
📄 rgephyreg.h(9.11 KB)
📄 rlphy.c(7.26 KB)
📄 rlswitch.c(11.82 KB)
📄 smcphy.c(6.26 KB)
📄 smscphy.c(5.49 KB)
📄 tdkphy.c(6.02 KB)
📄 tdkphyreg.h(2.67 KB)
📄 tiphy.h(2.61 KB)
📄 truephy.c(8.25 KB)
📄 truephyreg.h(2.63 KB)
📄 ukphy.c(4.79 KB)
📄 ukphy_subr.c(4.26 KB)
📄 vscphy.c(6.57 KB)
📄 xmphy.c(6.98 KB)
📄 xmphyreg.h(5.31 KB)

Editing: jmphyreg.h

/*-
 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
 *
 * Copyright (c) 2008, Pyun YongHyeon
 * All rights reserved.
 *              
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:             
 * 1. Redistributions of source code must retain the above copyright
 *    notice unmodified, this list of conditions, and the following
 *    disclaimer.  
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * $FreeBSD$
 */

#ifndef	_DEV_MII_JMPHYREG_H_
#define	_DEV_MII_JMPHYREG_H_

/*
 * Registers for the JMicron JMC250 Gigabit PHY.
 */

/* PHY specific status register. */
#define JMPHY_SSR			0x11
#define JMPHY_SSR_SPEED_1000		0x8000
#define JMPHY_SSR_SPEED_100		0x4000
#define JMPHY_SSR_SPEED_10		0x0000
#define JMPHY_SSR_SPEED_MASK		0xC000
#define JMPHY_SSR_DUPLEX		0x2000
#define JMPHY_SSR_SPD_DPLX_RESOLVED	0x0800
#define JMPHY_SSR_LINK_UP		0x0400
#define JMPHY_SSR_MDI_XOVER		0x0040
#define	JMPHY_SSR_INV_POLARITY		0x0002

/* PHY specific cable length status register. */
#define	JMPHY_SCL			0x17
#define	JMPHY_SCL_CHAN_D_MASK		0xF000
#define	JMPHY_SCL_CHAN_C_MASK		0x0F00
#define	JMPHY_SCL_CHAN_B_MASK		0x00F0
#define	JMPHY_SCL_CHAN_A_MASK		0x000F
#define	JMPHY_SCL_LEN_35		0
#define	JMPHY_SCL_LEN_40		1
#define	JMPHY_SCL_LEN_50		2
#define	JMPHY_SCL_LEN_60		3
#define	JMPHY_SCL_LEN_70		4
#define	JMPHY_SCL_LEN_80		5
#define	JMPHY_SCL_LEN_90		6
#define	JMPHY_SCL_LEN_100		7
#define	JMPHY_SCL_LEN_110		8
#define	JMPHY_SCL_LEN_120		9
#define	JMPHY_SCL_LEN_130		10
#define	JMPHY_SCL_LEN_140		11
#define	JMPHY_SCL_LEN_150		12
#define	JMPHY_SCL_LEN_160		13
#define	JMPHY_SCL_LEN_170		14
#define	JMPHY_SCL_RSVD			15

/* PHY specific LED control register 1. */
#define	JMPHY_LED_CTL1			0x18
#define	JMPHY_LED_BLINK_42MS		0x0000
#define	JMPHY_LED_BLINK_84MS		0x2000
#define	JMPHY_LED_BLINK_170MS		0x4000
#define	JMPHY_LED_BLINK_340MS		0x6000
#define	JMPHY_LED_BLINK_670MS		0x8000
#define	JMPHY_LED_BLINK_MASK		0xE000
#define	JMPHY_LED_FLP_GAP_MASK		0x1F00
#define	JMPHY_LED_FLP_GAP_DEFULT	0x1000
#define	JMPHY_LED2_POLARITY_MASK	0x0030
#define	JMPHY_LED1_POLARITY_MASK	0x000C
#define	JMPHY_LED0_POLARITY_MASK	0x0003
#define	JMPHY_LED_ON_LO_OFF_HI		0
#define	JMPHY_LED_ON_HI_OFF_HI		1
#define	JMPHY_LED_ON_LO_OFF_TS		2
#define	JMPHY_LED_ON_HI_OFF_TS		3

/* PHY specific LED control register 2. */
#define	JMPHY_LED_CTL2			0x19
#define	JMPHY_LED_NO_STRETCH		0x0000
#define	JMPHY_LED_STRETCH_42MS		0x2000
#define	JMPHY_LED_STRETCH_84MS		0x4000
#define	JMPHY_LED_STRETCH_170MS		0x6000
#define	JMPHY_LED_STRETCH_340MS		0x8000
#define	JMPHY_LED_STRETCH_670MS		0xB000
#define	JMPHY_LED_STRETCH_1300MS	0xC000
#define	JMPHY_LED_STRETCH_2700MS	0xE000
#define	JMPHY_LED2_MODE_MASK		0x0F00
#define	JMPHY_LED1_MODE_MASK		0x00F0
#define	JMPHY_LED0_MODE_MASK		0x000F

/* PHY specific test mode control register. */
#define	JMPHY_TMCTL			0x1A
#define	JMPHY_TMCTL_SLEEP_ENB		0x1000

/* PHY specific configuration register. */
#define	JMPHY_SPEC_ADDR			0x1E
#define	JMPHY_SPEC_ADDR_READ		0x4000
#define	JMPHY_SPEC_ADDR_WRITE		0x8000

#define	JMPHY_SPEC_DATA			0x1F

#define	JMPHY_EXT_COMM_2		0x32

#endif	/* _DEV_MII_JMPHYREG_H_ */

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