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k3-am65-main.dtsi
(25.09 KB)
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k3-am65-mcu.dtsi
(7.13 KB)
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k3-am65-wakeup.dtsi
(2.47 KB)
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k3-am65.dtsi
(4.26 KB)
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k3-am654-base-board.dts
(11.14 KB)
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k3-am654-industrial-thermal.dtsi
(1 KB)
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k3-am654.dtsi
(2.18 KB)
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k3-j721e-common-proc-board.dts
(14.49 KB)
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k3-j721e-main.dtsi
(37.18 KB)
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k3-j721e-mcu-wakeup.dtsi
(9.03 KB)
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k3-j721e-som-p0.dtsi
(1.93 KB)
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k3-j721e.dtsi
(5.6 KB)
Editing: k3-am65-mcu.dtsi
// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for AM6 SoC Family MCU Domain peripherals * * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu { mcu_conf: scm_conf@40f00000 { compatible = "syscon", "simple-mfd"; reg = <0x0 0x40f00000 0x0 0x20000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x40f00000 0x20000>; phy_gmii_sel: phy@4040 { compatible = "ti,am654-phy-gmii-sel"; reg = <0x4040 0x4>; #phy-cells = <1>; }; }; mcu_uart0: serial@40a00000 { compatible = "ti,am654-uart"; reg = <0x00 0x40a00000 0x00 0x100>; reg-shift = <2>; reg-io-width = <4>; interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <96000000>; current-speed = <115200>; power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; }; mcu_ram: sram@41c00000 { compatible = "mmio-sram"; reg = <0x00 0x41c00000 0x00 0x80000>; ranges = <0x0 0x00 0x41c00000 0x80000>; #address-cells = <1>; #size-cells = <1>; }; mcu_i2c0: i2c@40b00000 { compatible = "ti,am654-i2c", "ti,omap4-i2c"; reg = <0x0 0x40b00000 0x0 0x100>; interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "fck"; clocks = <&k3_clks 114 1>; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; }; mcu_spi0: spi@40300000 { compatible = "ti,am654-mcspi","ti,omap4-mcspi"; reg = <0x0 0x40300000 0x0 0x400>; interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 142 1>; power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; }; mcu_spi1: spi@40310000 { compatible = "ti,am654-mcspi","ti,omap4-mcspi"; reg = <0x0 0x40310000 0x0 0x400>; interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 143 1>; power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; }; mcu_spi2: spi@40320000 { compatible = "ti,am654-mcspi","ti,omap4-mcspi"; reg = <0x0 0x40320000 0x0 0x400>; interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 144 1>; power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; }; tscadc0: tscadc@40200000 { compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; reg = <0x0 0x40200000 0x0 0x1000>; interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 0 2>; assigned-clocks = <&k3_clks 0 2>; assigned-clock-rates = <60000000>; clock-names = "adc_tsc_fck"; dmas = <&mcu_udmap 0x7100>, <&mcu_udmap 0x7101 >; dma-names = "fifo0", "fifo1"; adc { #io-channel-cells = <1>; compatible = "ti,am654-adc", "ti,am3359-adc"; }; }; tscadc1: tscadc@40210000 { compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; reg = <0x0 0x40210000 0x0 0x1000>; interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; clocks = <&k3_clks 1 2>; assigned-clocks = <&k3_clks 1 2>; assigned-clock-rates = <60000000>; clock-names = "adc_tsc_fck"; dmas = <&mcu_udmap 0x7102>, <&mcu_udmap 0x7103>; dma-names = "fifo0", "fifo1"; adc { #io-channel-cells = <1>; compatible = "ti,am654-adc", "ti,am3359-adc"; }; }; mcu_navss { compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; ranges; dma-coherent; dma-ranges; ti,sci-dev-id = <119>; mcu_ringacc: ringacc@2b800000 { compatible = "ti,am654-navss-ringacc"; reg = <0x0 0x2b800000 0x0 0x400000>, <0x0 0x2b000000 0x0 0x400000>, <0x0 0x28590000 0x0 0x100>, <0x0 0x2a500000 0x0 0x40000>; reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,dma-ring-reset-quirk; ti,sci = <&dmsc>; ti,sci-dev-id = <195>; msi-parent = <&inta_main_udmass>; }; mcu_udmap: dma-controller@285c0000 { compatible = "ti,am654-navss-mcu-udmap"; reg = <0x0 0x285c0000 0x0 0x100>, <0x0 0x2a800000 0x0 0x40000>, <0x0 0x2aa00000 0x0 0x40000>; reg-names = "gcfg", "rchanrt", "tchanrt"; msi-parent = <&inta_main_udmass>; #dma-cells = <1>; ti,sci = <&dmsc>; ti,sci-dev-id = <194>; ti,ringacc = <&mcu_ringacc>; ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */ <0xd>; /* TX_CHAN */ ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */ <0xa>; /* RX_CHAN */ ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */ }; }; fss: fss@47000000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; ospi0: spi@47040000 { compatible = "ti,am654-ospi", "cdns,qspi-nor"; reg = <0x0 0x47040000 0x0 0x100>, <0x5 0x00000000 0x1 0x0000000>; interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,trigger-address = <0x0>; clocks = <&k3_clks 248 0>; assigned-clocks = <&k3_clks 248 0>; assigned-clock-parents = <&k3_clks 248 2>; assigned-clock-rates = <166666666>; power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; }; ospi1: spi@47050000 { compatible = "ti,am654-ospi", "cdns,qspi-nor"; reg = <0x0 0x47050000 0x0 0x100>, <0x7 0x00000000 0x1 0x00000000>; interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,trigger-address = <0x0>; clocks = <&k3_clks 249 6>; power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; }; }; mcu_cpsw: ethernet@46000000 { compatible = "ti,am654-cpsw-nuss"; #address-cells = <2>; #size-cells = <2>; reg = <0x0 0x46000000 0x0 0x200000>; reg-names = "cpsw_nuss"; ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; dma-coherent; clocks = <&k3_clks 5 10>; clock-names = "fck"; power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>; dmas = <&mcu_udmap 0xf000>, <&mcu_udmap 0xf001>, <&mcu_udmap 0xf002>, <&mcu_udmap 0xf003>, <&mcu_udmap 0xf004>, <&mcu_udmap 0xf005>, <&mcu_udmap 0xf006>, <&mcu_udmap 0xf007>, <&mcu_udmap 0x7000>; dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", "rx"; ethernet-ports { #address-cells = <1>; #size-cells = <0>; cpsw_port1: port@1 { reg = <1>; ti,mac-only; label = "port1"; ti,syscon-efuse = <&mcu_conf 0x200>; phys = <&phy_gmii_sel 1>; }; }; davinci_mdio: mdio@f00 { compatible = "ti,cpsw-mdio","ti,davinci_mdio"; reg = <0x0 0xf00 0x0 0x100>; #address-cells = <1>; #size-cells = <0>; clocks = <&k3_clks 5 10>; clock-names = "fck"; bus_freq = <1000000>; }; cpts@3d000 { compatible = "ti,am65-cpts"; reg = <0x0 0x3d000 0x0 0x400>; clocks = <&mcu_cpsw_cpts_mux>; clock-names = "cpts"; interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "cpts"; ti,cpts-ext-ts-inputs = <4>; ti,cpts-periodic-outputs = <2>; mcu_cpsw_cpts_mux: refclk-mux { #clock-cells = <0>; clocks = <&k3_clks 118 5>, <&k3_clks 118 11>, <&k3_clks 118 6>, <&k3_clks 118 3>, <&k3_clks 118 8>, <&k3_clks 118 14>, <&k3_clks 120 3>, <&k3_clks 121 3>; assigned-clocks = <&mcu_cpsw_cpts_mux>; assigned-clock-parents = <&k3_clks 118 5>; }; }; }; };
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