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altera-fpga2sdram-bridge.txt
(353 B)
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altera-freeze-bridge.txt
(697 B)
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altera-hps2fpga-bridge.txt
(1.02 KB)
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altera-passive-serial.txt
(988 B)
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altera-pr-ip.txt
(276 B)
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altera-socfpga-a10-fpga-mgr.txt
(629 B)
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altera-socfpga-fpga-mgr.txt
(533 B)
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fpga-bridge.txt
(367 B)
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fpga-region.txt
(17.25 KB)
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intel-stratix10-soc-fpga-mgr.txt
(372 B)
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lattice-ice40-fpga-mgr.txt
(729 B)
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lattice-machxo2-spi.txt
(656 B)
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xilinx-pr-decoupler.txt
(1.12 KB)
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xilinx-slave-serial.txt
(1.62 KB)
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xilinx-zynq-fpga-mgr.txt
(560 B)
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xlnx,zynqmp-pcap-fpga.txt
(641 B)
Editing: lattice-ice40-fpga-mgr.txt
Lattice iCE40 FPGA Manager Required properties: - compatible: Should contain "lattice,ice40-fpga-mgr" - reg: SPI chip select - spi-max-frequency: Maximum SPI frequency (>=1000000, <=25000000) - cdone-gpios: GPIO input connected to CDONE pin - reset-gpios: Active-low GPIO output connected to CRESET_B pin. Note that unless the GPIO is held low during startup, the FPGA will enter Master SPI mode and drive SCK with a clock signal potentially jamming other devices on the bus until the firmware is loaded. Example: fpga: fpga@0 { compatible = "lattice,ice40-fpga-mgr"; reg = <0>; spi-max-frequency = <1000000>; cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>; };
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