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📄 83xx-512x-pci.txt(1.27 KB)
📄 aardvark-pci.txt(1.92 KB)
📄 altera-pcie-msi.txt(856 B)
📄 altera-pcie.txt(1.82 KB)
📄 amlogic,meson-pcie.txt(2.19 KB)
📄 axis,artpec6-pcie.txt(1.93 KB)
📄 brcm,iproc-pcie.txt(4.43 KB)
📄 brcm,stb-pcie.yaml(2.4 KB)
📄 cdns,cdns-pcie-ep.yaml(1007 B)
📄 cdns,cdns-pcie-host.yaml(1.75 KB)
📄 cdns-pcie-ep.yaml(536 B)
📄 cdns-pcie-host.yaml(890 B)
📄 cdns-pcie.yaml(523 B)
📄 designware-pcie.txt(2.83 KB)
📄 faraday,ftpci100.txt(4.7 KB)
📄 fsl,imx6q-pcie.txt(3.84 KB)
📄 fsl,pci.txt(811 B)
📄 hisilicon-histb-pcie.txt(2.42 KB)
📄 hisilicon-pcie.txt(1.53 KB)
📄 host-generic-pci.yaml(6.04 KB)
📄 intel-gw-pcie.yaml(2.89 KB)
📄 kirin-pcie.txt(1.78 KB)
📄 layerscape-pci.txt(2.73 KB)
📄 layerscape-pcie-gen4.txt(2.32 KB)
📄 loongson.yaml(1.34 KB)
📄 mediatek-pcie.txt(8.93 KB)
📄 mobiveil-pcie.txt(2.43 KB)
📄 mvebu-pci.txt(9.8 KB)
📄 nvidia,tegra194-pcie.txt(9.85 KB)
📄 nvidia,tegra20-pcie.txt(20.21 KB)
📄 pci-armada8k.txt(1.66 KB)
📄 pci-ep.yaml(850 B)
📄 pci-iommu.txt(3.68 KB)
📄 pci-keystone.txt(4.36 KB)
📄 pci-msi.txt(5.05 KB)
📄 pci-rcar-gen2.txt(2.72 KB)
📄 pci.txt(3.56 KB)
📄 pcie-al.txt(1.4 KB)
📄 qcom,pcie.txt(9.54 KB)
📄 ralink,rt3883-pci.txt(4.6 KB)
📄 rcar-pci-ep.yaml(1.75 KB)
📄 rcar-pci.txt(2.9 KB)
📄 rockchip-pcie-ep.txt(2.23 KB)
📄 rockchip-pcie-host.txt(4.89 KB)
📄 samsung,exynos5440-pcie.txt(1.67 KB)
📄 socionext,uniphier-pcie-ep.yaml(1.83 KB)
📄 spear13xx-pcie.txt(484 B)
📄 tango-pcie.txt(804 B)
📄 ti,j721e-pci-ep.yaml(2.15 KB)
📄 ti,j721e-pci-host.yaml(2.67 KB)
📄 ti-pci.txt(4 KB)
📄 uniphier-pcie.txt(2.83 KB)
📄 v3-v360epc-pci.txt(3.17 KB)
📄 versatile.yaml(2.08 KB)
📄 xgene-pci-msi.txt(2.13 KB)
📄 xgene-pci.txt(1.84 KB)
📄 xilinx-nwl-pcie.txt(2.67 KB)
📄 xilinx-pcie.txt(2.73 KB)
📄 xilinx-versal-cpm.yaml(2.83 KB)

Editing: layerscape-pcie-gen4.txt

NXP Layerscape PCIe Gen4 controller

This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all
the common properties defined in mobiveil-pcie.txt.

Required properties:
- compatible: should contain the platform identifier such as:
  "fsl,lx2160a-pcie"
- reg: base addresses and lengths of the PCIe controller register blocks.
  "csr_axi_slave": Bridge config registers
  "config_axi_slave": PCIe controller registers
- interrupts: A list of interrupt outputs of the controller. Must contain an
  entry for each entry in the interrupt-names property.
- interrupt-names: It could include the following entries:
  "intr": The interrupt that is asserted for controller interrupts
  "aer": Asserted for aer interrupt when chip support the aer interrupt with
	 none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
  "pme": Asserted for pme interrupt when chip support the pme interrupt with
	 none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
- dma-coherent: Indicates that the hardware IP block can ensure the coherency
  of the data transferred from/to the IP block. This can avoid the software
  cache flush/invalid actions, and improve the performance significantly.
- msi-parent : See the generic MSI binding described in
  Documentation/devicetree/bindings/interrupt-controller/msi.txt.

Example:

pcie@3400000 {
		compatible = "fsl,lx2160a-pcie";
		reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
		       0x80 0x00000000 0x0 0x00001000>; /* configuration space */
		reg-names = "csr_axi_slave", "config_axi_slave";
		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
		interrupt-names = "aer", "pme", "intr";
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		apio-wins = <8>;
		ppio-wins = <8>;
		dma-coherent;
		bus-range = <0x0 0xff>;
		msi-parent = <&its>;
		ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
				<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
				<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
				<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	};

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Editing: layerscape-pcie-gen4.txt

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