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_align.h
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_bus.h
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_inttypes.h
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_limits.h
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_stdint.h
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_types.h
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abi.h
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asm.h
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atomic.h
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bootinfo.h
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bus.h
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bus_dma.h
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cache.h
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cache_mipsNN.h
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cache_r4k.h
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cca.h
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cdefs.h
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clock.h
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counter.h
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cpu.h
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cpufunc.h
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cpuinfo.h
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cpuregs.h
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db_machdep.h
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dump.h
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efi.h
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elf.h
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endian.h
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exec.h
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fdt.h
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float.h
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floatingpoint.h
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fls64.h
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fpu.h
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frame.h
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gdb_machdep.h
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hwfunc.h
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ieee.h
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ieeefp.h
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in_cksum.h
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intr.h
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intr_machdep.h
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kdb.h
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limits.h
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locore.h
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md_var.h
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memdev.h
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metadata.h
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minidump.h
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mips_opcode.h
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octeon_cop2.h
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ofw_machdep.h
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param.h
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pcb.h
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pcpu.h
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pcpu_aux.h
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pmap.h
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pmc_mdep.h
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proc.h
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procctl.h
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profile.h
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pte.h
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ptrace.h
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reg.h
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regdef.h
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regnum.h
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reloc.h
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resource.h
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runq.h
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sc_machdep.h
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setjmp.h
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sf_buf.h
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sigframe.h
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signal.h
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smp.h
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stdarg.h
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sysarch.h
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tlb.h
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tls.h
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trap.h
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ucontext.h
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vdso.h
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vm.h
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vmparam.h
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Editing: locore.h
/* $NetBSD: locore.h,v 1.78 2007/10/17 19:55:36 garbled Exp $ */ /* * Copyright 1996 The Board of Trustees of The Leland Stanford * Junior University. All Rights Reserved. * * Permission to use, copy, modify, and distribute this * software and its documentation for any purpose and without * fee is hereby granted, provided that the above copyright * notice appear in all copies. Stanford University * makes no representations about the suitability of this * software for any purpose. It is provided "as is" without * express or implied warranty. * * $FreeBSD$ */ /* * Jump table for MIPS cpu locore functions that are implemented * differently on different generations, or instruction-level * archtecture (ISA) level, the Mips family. * * We currently provide support for MIPS I and MIPS III. */ #ifndef _MIPS_LOCORE_H #define _MIPS_LOCORE_H #include <machine/cpufunc.h> #include <machine/cpuregs.h> #include <machine/frame.h> #include <machine/md_var.h> /* * CPU identification, from PRID register. */ #define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) #define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) /* pre-MIPS32/64 */ #define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) #define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) #define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) /* MIPS32/64 */ #define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ #define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */ #define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ #define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */ #define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */ #define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */ #define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */ #define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */ #define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */ #define MIPS_PRID_CID_LSI 0x08 /* LSI */ /* 0x09 unannounced */ /* 0x0a unannounced */ #define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */ #define MIPS_PRID_CID_RMI 0x0c /* RMI */ #define MIPS_PRID_CID_CAVIUM 0x0d /* Cavium */ #define MIPS_PRID_CID_INGENIC 0xe1 /* Ingenic */ #define MIPS_PRID_CID_INGENIC2 0xd1 /* Ingenic */ #define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */ #endif /* _MIPS_LOCORE_H */
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