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📄 acphy.c(6.8 KB)
📄 acphyreg.h(3.39 KB)
📄 amphy.c(5.68 KB)
📄 amphyreg.h(3.71 KB)
📄 atphy.c(9.06 KB)
📄 atphyreg.h(2.46 KB)
📄 axphy.c(4.27 KB)
📄 bmtphy.c(7.2 KB)
📄 bmtphyreg.h(7.51 KB)
📄 brgphy.c(32.55 KB)
📄 brgphyreg.h(18.76 KB)
📄 ciphy.c(9.45 KB)
📄 ciphyreg.h(16.78 KB)
📄 e1000phy.c(13.82 KB)
📄 e1000phyreg.h(13.79 KB)
📄 gentbi.c(7.33 KB)
📄 icsphy.c(6.76 KB)
📄 icsphyreg.h(4.99 KB)
📄 ip1000phy.c(8.88 KB)
📄 ip1000phyreg.h(6.73 KB)
📄 jmphy.c(8.38 KB)
📄 jmphyreg.h(4.07 KB)
📄 lxtphy.c(7.35 KB)
📄 lxtphyreg.h(3.64 KB)
📄 micphy.c(9.27 KB)
📄 mii.c(16.35 KB)
📄 mii.h(10.3 KB)
📄 mii_bitbang.c(4.46 KB)
📄 mii_bitbang.h(2.36 KB)
📄 mii_fdt.c(6.02 KB)
📄 mii_fdt.h(2.9 KB)
📄 mii_physubr.c(17.29 KB)
📄 miibus_if.m(533 B)
📄 miidevs(16.37 KB)
📄 miivar.h(9.61 KB)
📄 nsgphy.c(6.74 KB)
📄 nsgphyreg.h(3.43 KB)
📄 nsphy.c(9.02 KB)
📄 nsphyreg.h(4.39 KB)
📄 nsphyter.c(7.77 KB)
📄 nsphyterreg.h(8.3 KB)
📄 pnaphy.c(4.19 KB)
📄 qsphy.c(6.26 KB)
📄 qsphyreg.h(3.74 KB)
📄 rdcphy.c(5.91 KB)
📄 rdcphyreg.h(2.67 KB)
📄 rgephy.c(15.06 KB)
📄 rgephyreg.h(9.11 KB)
📄 rlphy.c(7.26 KB)
📄 rlswitch.c(11.82 KB)
📄 smcphy.c(6.26 KB)
📄 smscphy.c(5.49 KB)
📄 tdkphy.c(6.02 KB)
📄 tdkphyreg.h(2.67 KB)
📄 tiphy.h(2.61 KB)
📄 truephy.c(8.25 KB)
📄 truephyreg.h(2.63 KB)
📄 ukphy.c(4.79 KB)
📄 ukphy_subr.c(4.26 KB)
📄 vscphy.c(6.57 KB)
📄 xmphy.c(6.98 KB)
📄 xmphyreg.h(5.31 KB)

Editing: mii_bitbang.c

/*	$NetBSD: mii_bitbang.c,v 1.12 2008/05/04 17:06:09 xtraeme Exp $	*/

/*-
 * SPDX-License-Identifier: BSD-2-Clause-NetBSD
 *
 * Copyright (c) 1999 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
 * NASA Ames Research Center.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following didevlaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following didevlaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Common module for bit-bang'ing the MII.
 */

#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/module.h>

#include <dev/mii/mii.h>
#include <dev/mii/mii_bitbang.h>

MODULE_VERSION(mii_bitbang, 1);

static void mii_bitbang_sendbits(device_t dev, mii_bitbang_ops_t ops,
    uint32_t data, int nbits);

#define	MWRITE(x)							\
do {									\
	ops->mbo_write(dev, (x));					\
	DELAY(1);							\
} while (/* CONSTCOND */ 0)

#define	MREAD		ops->mbo_read(dev)

#define	MDO		ops->mbo_bits[MII_BIT_MDO]
#define	MDI		ops->mbo_bits[MII_BIT_MDI]
#define	MDC		ops->mbo_bits[MII_BIT_MDC]
#define	MDIRPHY		ops->mbo_bits[MII_BIT_DIR_HOST_PHY]
#define	MDIRHOST	ops->mbo_bits[MII_BIT_DIR_PHY_HOST]

/*
 * mii_bitbang_sync:
 *
 *	Synchronize the MII.
 */
void
mii_bitbang_sync(device_t dev, mii_bitbang_ops_t ops)
{
	int i;
	uint32_t v;

v = MDIRPHY | MDO;

MWRITE(v);
	for (i = 0; i < 32; i++) {
		MWRITE(v | MDC);
		MWRITE(v);
	}
}

/*
 * mii_bitbang_sendbits:
 *
 *	Send a series of bits to the MII.
 */
static void
mii_bitbang_sendbits(device_t dev, mii_bitbang_ops_t ops, uint32_t data,
    int nbits)
{
	int i;
	uint32_t v;

v = MDIRPHY;
	MWRITE(v);

for (i = 1 << (nbits - 1); i != 0; i >>= 1) {
		if (data & i)
			v |= MDO;
		else
			v &= ~MDO;
		MWRITE(v);
		MWRITE(v | MDC);
		MWRITE(v);
	}
}

/*
 * mii_bitbang_readreg:
 *
 *	Read a PHY register by bit-bang'ing the MII.
 */
int
mii_bitbang_readreg(device_t dev, mii_bitbang_ops_t ops, int phy, int reg)
{
	int i, error, val;

mii_bitbang_sync(dev, ops);

mii_bitbang_sendbits(dev, ops, MII_COMMAND_START, 2);
	mii_bitbang_sendbits(dev, ops, MII_COMMAND_READ, 2);
	mii_bitbang_sendbits(dev, ops, phy, 5);
	mii_bitbang_sendbits(dev, ops, reg, 5);

/* Switch direction to PHY->host, without a clock transition. */
	MWRITE(MDIRHOST);

/* Turnaround clock. */
	MWRITE(MDIRHOST | MDC);
	MWRITE(MDIRHOST);

/* Check for error. */
	error = MREAD & MDI;

/* Idle clock. */
	MWRITE(MDIRHOST | MDC);
	MWRITE(MDIRHOST);

val = 0;
	for (i = 0; i < 16; i++) {
		val <<= 1;
		/* Read data prior to clock low-high transition. */
		if (error == 0 && (MREAD & MDI) != 0)
			val |= 1;

MWRITE(MDIRHOST | MDC);
		MWRITE(MDIRHOST);
	}

/* Set direction to host->PHY, without a clock transition. */
	MWRITE(MDIRPHY);

return (error != 0 ? 0 : val);
}

/*
 * mii_bitbang_writereg:
 *
 *	Write a PHY register by bit-bang'ing the MII.
 */
void
mii_bitbang_writereg(device_t dev, mii_bitbang_ops_t ops, int phy, int reg,
    int val)
{

mii_bitbang_sync(dev, ops);

mii_bitbang_sendbits(dev, ops, MII_COMMAND_START, 2);
	mii_bitbang_sendbits(dev, ops, MII_COMMAND_WRITE, 2);
	mii_bitbang_sendbits(dev, ops, phy, 5);
	mii_bitbang_sendbits(dev, ops, reg, 5);
	mii_bitbang_sendbits(dev, ops, MII_COMMAND_ACK, 2);
	mii_bitbang_sendbits(dev, ops, val, 16);

MWRITE(MDIRPHY);
}

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Editing: mii_bitbang.c

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