003 File Manager
Current Path:
/usr/src/sys/contrib/device-tree/Bindings/memory-controllers/fsl
usr
/
src
/
sys
/
contrib
/
device-tree
/
Bindings
/
memory-controllers
/
fsl
/
📁
..
📄
ddr.txt
(738 B)
📄
ifc.txt
(2.36 KB)
📄
imx8m-ddrc.yaml
(1.84 KB)
📄
mmdc.txt
(955 B)
📄
mmdc.yaml
(1.03 KB)
Editing: mmdc.txt
Freescale Multi Mode DDR controller (MMDC) Required properties : - compatible : should be one of following: for i.MX6Q/i.MX6DL: - "fsl,imx6q-mmdc"; for i.MX6QP: - "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc"; for i.MX6SL: - "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; for i.MX6SLL: - "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc"; for i.MX6SX: - "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; for i.MX6UL/i.MX6ULL/i.MX6ULZ: - "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; for i.MX7ULP: - "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc"; - reg : address and size of MMDC DDR controller registers Optional properties : - clocks : the clock provided by the SoC to access the MMDC registers Example : mmdc0: memory-controller@21b0000 { /* MMDC0 */ compatible = "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>; }; mmdc1: memory-controller@21b4000 { /* MMDC1 */ compatible = "fsl,imx6q-mmdc"; reg = <0x021b4000 0x4000>; status = "disabled"; };
Upload File
Create Folder