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usr / src / sys / contrib / device-tree / Bindings / powerpc / fsl /

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📄 cache_sram.txt(559 B)
📄 ccf.txt(1.37 KB)
📄 cpus.txt(1.43 KB)
📄 dcsr.txt(10.72 KB)
📄 diu.txt(847 B)
📄 dma.txt(6.56 KB)
📄 ecm.txt(1.81 KB)
📄 interlaken-lac.txt(8.59 KB)
📄 l2cache.txt(2.03 KB)
📄 lbc.txt(1.11 KB)
📄 mcm.txt(1.81 KB)
📄 mcu-mpc8349emitx.txt(428 B)
📄 mpc5121-psc.txt(2.4 KB)
📄 mpc512x_lpbfifo.txt(669 B)
📄 mpc5200.txt(8.6 KB)
📄 mpic-msgr.txt(2.35 KB)
📄 mpic-timer.txt(1.14 KB)
📄 mpic.txt(7.33 KB)
📄 msi-pic.txt(4.38 KB)
📄 pamu.txt(4.78 KB)
📄 pmc.txt(2.48 KB)
📄 raideng.txt(2.47 KB)
📄 scfg.txt(451 B)
📄 srio-rmu.txt(5.12 KB)
📄 srio.txt(3.34 KB)

Editing: mpic-timer.txt

* Freescale MPIC timers

Required properties:
- compatible: "fsl,mpic-global-timer"

- reg : Contains two regions.  The first is the main timer register bank
  (GTCCRxx, GTBCRxx, GTVPRxx, GTDRxx).  The second is the timer control
  register (TCRx) for the group.

- fsl,available-ranges: use <start count> style section to define which
  timer interrupts can be used.  This property is optional; without this,
  all timers within the group can be used.

- interrupts: one interrupt per timer in the group, in order, starting
  with timer zero.  If timer-available-ranges is present, only the
  interrupts that correspond to available timers shall be present.

Example:
	/* Note that this requires #interrupt-cells to be 4 */
	timer0: timer@41100 {
		compatible = "fsl,mpic-global-timer";
		reg = <0x41100 0x100 0x41300 4>;

/* Another AMP partition is using timers 0 and 1 */
		fsl,available-ranges = <2 2>;

interrupts = <2 0 3 0
		              3 0 3 0>;
	};

timer1: timer@42100 {
		compatible = "fsl,mpic-global-timer";
		reg = <0x42100 0x100 0x42300 4>;
		interrupts = <4 0 3 0
		              5 0 3 0
		              6 0 3 0
		              7 0 3 0>;
	};

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Editing: mpic-timer.txt

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