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mt2712-evb.dts
(5.12 KB)
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mt2712-pinfunc.h
(60.45 KB)
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mt2712e.dtsi
(28.29 KB)
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mt6358.dtsi
(9.81 KB)
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mt6380.dtsi
(2 KB)
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mt6755-evb.dts
(463 B)
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mt6755.dtsi
(3.2 KB)
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mt6795-evb.dts
(536 B)
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mt6795.dtsi
(3.86 KB)
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mt6797-evb.dts
(496 B)
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mt6797-x20-dev.dts
(1.24 KB)
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mt6797.dtsi
(11.12 KB)
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mt7622-bananapi-bpi-r64.dts
(8.79 KB)
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mt7622-rfb1.dts
(8.23 KB)
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mt7622.dtsi
(24.34 KB)
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mt8173-elm-hana-rev7.dts
(416 B)
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mt8173-elm-hana.dts
(297 B)
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mt8173-elm-hana.dtsi
(1.37 KB)
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mt8173-elm.dts
(324 B)
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mt8173-elm.dtsi
(25.29 KB)
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mt8173-evb.dts
(12.45 KB)
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mt8173-pinfunc.h
(34.53 KB)
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mt8173.dtsi
(40.14 KB)
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mt8183-evb.dts
(7.65 KB)
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mt8183-kukui-krane-sku176.dts
(403 B)
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mt8183-kukui-krane.dtsi
(4.83 KB)
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mt8183-kukui.dtsi
(15.51 KB)
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mt8183-pinfunc.h
(54.22 KB)
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mt8183.dtsi
(20.33 KB)
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mt8516-pinfunc.h
(34.35 KB)
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mt8516-pumpkin.dts
(349 B)
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mt8516.dtsi
(12.32 KB)
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pumpkin-common.dtsi
(4.11 KB)
Editing: mt6755.dtsi
/* * Copyright (c) 2016 MediaTek Inc. * Author: Mars.C <mars.cheng@mediatek.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> / { compatible = "mediatek,mt6755"; interrupt-parent = <&sysirq>; #address-cells = <2>; #size-cells = <2>; psci { compatible = "arm,psci-0.2"; method = "smc"; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x000>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x001>; }; cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x002>; }; cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x003>; }; cpu4: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x100>; }; cpu5: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x101>; }; cpu6: cpu@102 { device_type = "cpu"; compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x102>; }; cpu7: cpu@103 { device_type = "cpu"; compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x103>; }; }; uart_clk: dummy26m { compatible = "fixed-clock"; clock-frequency = <26000000>; #clock-cells = <0>; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; sysirq: intpol-controller@10200620 { compatible = "mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq"; interrupt-controller; #interrupt-cells = <3>; interrupt-parent = <&gic>; reg = <0 0x10200620 0 0x20>; }; gic: interrupt-controller@10231000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; interrupt-parent = <&gic>; interrupt-controller; reg = <0 0x10231000 0 0x1000>, <0 0x10232000 0 0x2000>, <0 0x10234000 0 0x2000>, <0 0x10236000 0 0x2000>; }; uart0: serial@11002000 { compatible = "mediatek,mt6755-uart", "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x400>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; clocks = <&uart_clk>; status = "disabled"; }; uart1: serial@11003000 { compatible = "mediatek,mt6755-uart", "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x400>; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; clocks = <&uart_clk>; status = "disabled"; }; };
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