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usr / src / sys / contrib / device-tree / src / arc /

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📄 abilis_tb100.dtsi(8.47 KB)
📄 abilis_tb100_dvk.dts(2.04 KB)
📄 abilis_tb101.dtsi(8.72 KB)
📄 abilis_tb101_dvk.dts(2.04 KB)
📄 abilis_tb10x.dtsi(5.66 KB)
📄 axc001.dtsi(2.97 KB)
📄 axc003.dtsi(3.78 KB)
📄 axc003_idu.dtsi(3.85 KB)
📄 axs101.dts(437 B)
📄 axs103.dts(476 B)
📄 axs103_idu.dts(507 B)
📄 axs10x_mb.dtsi(7.08 KB)
📄 eznps.dts(1.54 KB)
📄 haps_hs.dts(2.03 KB)
📄 haps_hs_idu.dts(1.46 KB)
📄 hsdk.dts(7.45 KB)
📄 nsim_700.dts(1.09 KB)
📄 nsimosci.dts(1.77 KB)
📄 nsimosci_hs.dts(1.83 KB)
📄 nsimosci_hs_idu.dts(2.02 KB)
📄 skeleton.dtsi(858 B)
📄 skeleton_hs.dtsi(905 B)
📄 skeleton_hs_idu.dtsi(1.06 KB)
📄 vdk_axc003.dtsi(1.29 KB)
📄 vdk_axc003_idu.dtsi(1.47 KB)
📄 vdk_axs10x_mb.dtsi(2.82 KB)
📄 vdk_hs38.dts(410 B)
📄 vdk_hs38_smp.dts(448 B)

Editing: nsimosci_hs.dts

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
 */
/dts-v1/;

/include/ "skeleton_hs.dtsi"

/ {
	model = "snps,nsimosci_hs";
	compatible = "snps,nsimosci_hs";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&core_intc>;

chosen {
		/* this is for console on PGU */
		/* bootargs = "console=tty0 consoleblank=0"; */
		/* this is for console on serial */
		bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24 print-fatal-signals=1";
	};

aliases {
		serial0 = &uart0;
	};

fpga {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;

/* child and parent address space 1:1 mapped */
		ranges;

core_clk: core_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <20000000>;
		};

core_intc: core-interrupt-controller {
			compatible = "snps,archs-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
		};

uart0: serial@f0000000 {
			compatible = "ns8250";
			reg = <0xf0000000 0x2000>;
			interrupts = <24>;
			clock-frequency = <3686400>;
			baud = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
			no-loopback-test = <1>;
		};

pguclk: pguclk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <25175000>;
		};

pgu@f9000000 {
			compatible = "snps,arcpgu";
			reg = <0xf9000000 0x400>;
			clocks = <&pguclk>;
			clock-names = "pxlclk";
		};

ps2: ps2@f9001000 {
			compatible = "snps,arc_ps2";
			reg = <0xf9000400 0x14>;
			interrupts = <27>;
			interrupt-names = "arc_ps2_irq";
		};

eth0: ethernet@f0003000 {
			compatible = "ezchip,nps-mgt-enet";
			reg = <0xf0003000 0x44>;
			interrupts = <25>;
		};

arcpct0: pct {
			compatible = "snps,archs-pct";
			#interrupt-cells = <1>;
			interrupts = <20>;
		};
	};
};

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Editing: nsimosci_hs.dts

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