003 File Manager
Current Path:
/usr/src/sys/contrib/device-tree/Bindings/display/tegra
usr
/
src
/
sys
/
contrib
/
device-tree
/
Bindings
/
display
/
tegra
/
📁
..
📄
nvidia,tegra114-mipi.txt
(1002 B)
📄
nvidia,tegra20-host1x.txt
(16.2 KB)
Editing: nvidia,tegra20-host1x.txt
NVIDIA Tegra host1x Required properties: - compatible: "nvidia,tegra<chip>-host1x" - reg: Physical base address and length of the controller's registers. For pre-Tegra186, one entry describing the whole register area. For Tegra186, one entry for each entry in reg-names: "vm" - VM region assigned to Linux "hypervisor" - Hypervisor region (only if Linux acts as hypervisor) - interrupts: The interrupt outputs from the controller. - #address-cells: The number of cells used to represent physical base addresses in the host1x address space. Should be 1. - #size-cells: The number of cells used to represent the size of an address range in the host1x address space. Should be 1. - ranges: The mapping of the host1x address space to the CPU address space. - clocks: Must contain one entry, for the module clock. See ../clocks/clock-bindings.txt for details. - resets: Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. - reset-names: Must include the following entries: - host1x The host1x top-level node defines a number of children, each representing one of the following host1x client modules: - mpe: video encoder Required properties: - compatible: "nvidia,tegra<chip>-mpe" - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt outputs from the controller. - clocks: Must contain one entry, for the module clock. See ../clocks/clock-bindings.txt for details. - resets: Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. - reset-names: Must include the following entries: - mpe - vi: video input Required properties: - compatible: "nvidia,tegra<chip>-vi" - reg: Physical base address and length of the controller registers. - interrupts: The interrupt outputs from the controller. - clocks: clocks: Must contain one entry, for the module clock. See ../clocks/clock-bindings.txt for details. - Tegra20/Tegra30/Tegra114/Tegra124: - resets: Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. - reset-names: Must include the following entries: - vi - Tegra210: - power-domains: Must include venc powergate node as vi is in VE partition. - Tegra210 has CSI part of VI sharing same host interface and register space. So, VI device node should have CSI child node. - csi: mipi csi interface to vi Required properties: - compatible: "nvidia,tegra210-csi" - reg: Physical base address offset to parent and length of the controller registers. - clocks: Must contain entries csi, cilab, cilcd, cile, csi_tpg clocks. See ../clocks/clock-bindings.txt for details. - power-domains: Must include sor powergate node as csicil is in SOR partition. - epp: encoder pre-processor Required properties: - compatible: "nvidia,tegra<chip>-epp" - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt outputs from the controller. - clocks: Must contain one entry, for the module clock. See ../clocks/clock-bindings.txt for details. - resets: Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. - reset-names: Must include the following entries: - epp - isp: image signal processor Required properties: - compatible: "nvidia,tegra<chip>-isp" - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt outputs from the controller. - clocks: Must contain one entry, for the module clock. See ../clocks/clock-bindings.txt for details. - resets: Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. - reset-names: Must include the following entries: - isp - gr2d: 2D graphics engine Required properties: - compatible: "nvidia,tegra<chip>-gr2d" - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt outputs from the controller. - clocks: Must contain one entry, for the module clock. See ../clocks/clock-bindings.txt for details. - resets: Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. - reset-names: Must include the following entries: - 2d - gr3d: 3D graphics engine Required properties: - compatible: "nvidia,tegra<chip>-gr3d" - reg: Physical base address and length of the controller's registers. - clocks: Must contain an entry for each entry in clock-names. See ../clocks/clock-bindings.txt for details. - clock-names: Must include the following entries: (This property may be omitted if the only clock in the list is "3d") - 3d This MUST be the first entry. - 3d2 (Only required on SoCs with two 3D clocks) - resets: Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. - reset-names: Must include the following entries: - 3d - 3d2 (Only required on SoCs with two 3D clocks) - dc: display controller Required properties: - compatible: "nvidia,tegra<chip>-dc" - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt outputs from the controller. - clocks: Must contain an entry for each entry in clock-names. See ../clocks/clock-bindings.txt for details. - clock-names: Must include the following entries: - dc This MUST be the first entry. - parent - resets: Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. - reset-names: Must include the following entries: - dc - nvidia,head: The number of the display controller head. This is used to setup the various types of output to receive video data from the given head. Each display controller node has a child node, named "rgb", that represents the RGB output associated with the controller. It can take the following optional properties: - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - nvidia,edid: supplies a binary EDID blob - nvidia,panel: phandle of a display panel - hdmi: High Definition Multimedia Interface Required properties: - compatible: "nvidia,tegra<chip>-hdmi" - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt outputs from the controller. - hdmi-supply: supply for the +5V HDMI connector pin - vdd-supply: regulator for supply voltage - pll-supply: regulator for PLL - clocks: Must contain an entry for each entry in clock-names. See ../clocks/clock-bindings.txt for details. - clock-names: Must include the following entries: - hdmi This MUST be the first entry. - parent - resets: Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. - reset-names: Must include the following entries: - hdmi Optional properties: - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - nvidia,edid: supplies a binary EDID blob - nvidia,panel: phandle of a display panel - tvo: TV encoder output Required properties: - compatible: "nvidia,tegra<chip>-tvo" - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt outputs from the controller. - clocks: Must contain one entry, for the module clock. See ../clocks/clock-bindings.txt for details. - dsi: display serial interface Required properties: - compatible: "nvidia,tegra<chip>-dsi" - reg: Physical base address and length of the controller's registers. - clocks: Must contain an entry for each entry in clock-names. See ../clocks/clock-bindings.txt for details. - clock-names: Must include the following entries: - dsi This MUST be the first entry. - lp - parent - resets: Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. - reset-names: Must include the following entries: - dsi - avdd-dsi-supply: phandle of a supply that powers the DSI controller - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying which pads are used by this DSI output and need to be calibrated. See also ../display/tegra/nvidia,tegra114-mipi.txt. Optional properties: - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - nvidia,edid: supplies a binary EDID blob - nvidia,panel: phandle of a display panel - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang up with in order to support up to 8 data lanes - sor: serial output resource Required properties: - compatible: Should be: - "nvidia,tegra124-sor": for Tegra124 and Tegra132 - "nvidia,tegra132-sor": for Tegra132 - "nvidia,tegra210-sor": for Tegra210 - "nvidia,tegra210-sor1": for Tegra210 - "nvidia,tegra186-sor": for Tegra186 - "nvidia,tegra186-sor1": for Tegra186 - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt outputs from the controller. - clocks: Must contain an entry for each entry in clock-names. See ../clocks/clock-bindings.txt for details. - clock-names: Must include the following entries: - sor: clock input for the SOR hardware - out: SOR output clock - parent: input for the pixel clock - dp: reference clock for the SOR clock - safe: safe reference for the SOR clock during power up For Tegra186 and later: - pad: SOR pad output clock (on Tegra186 and later) Obsolete: - source: source clock for the SOR clock (obsolete, use "out" instead) - resets: Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. - reset-names: Must include the following entries: - sor Required properties on Tegra186 and later: - nvidia,interface: index of the SOR interface Optional properties: - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - nvidia,edid: supplies a binary EDID blob - nvidia,panel: phandle of a display panel - nvidia,xbar-cfg: 5 cells containing the crossbar configuration. Each lane of the SOR, identified by the cell's index, is mapped via the crossbar to the pad specified by the cell's value. Optional properties when driving an eDP output: - nvidia,dpaux: phandle to a DispayPort AUX interface - dpaux: DisplayPort AUX interface - compatible : Should contain one of the following: - "nvidia,tegra124-dpaux": for Tegra124 and Tegra132 - "nvidia,tegra210-dpaux": for Tegra210 - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt outputs from the controller. - clocks: Must contain an entry for each entry in clock-names. See ../clocks/clock-bindings.txt for details. - clock-names: Must include the following entries: - dpaux: clock input for the DPAUX hardware - parent: reference clock - resets: Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. - reset-names: Must include the following entries: - dpaux - vdd-supply: phandle of a supply that powers the DisplayPort link - i2c-bus: Subnode where I2C slave devices are listed. This subnode must be always present. If there are no I2C slave devices, an empty node should be added. See ../../i2c/i2c.txt for more information. See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information regarding the DPAUX pad controller bindings. - vic: Video Image Compositor - compatible : "nvidia,tegra<chip>-vic" - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt outputs from the controller. - clocks: Must contain an entry for each entry in clock-names. See ../clocks/clock-bindings.txt for details. - clock-names: Must include the following entries: - vic: clock input for the VIC hardware - resets: Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. - reset-names: Must include the following entries: - vic Example: / { ... host1x { compatible = "nvidia,tegra20-host1x", "simple-bus"; reg = <0x50000000 0x00024000>; interrupts = <0 65 0x04 /* mpcore syncpt */ 0 67 0x04>; /* mpcore general */ clocks = <&tegra_car TEGRA20_CLK_HOST1X>; resets = <&tegra_car 28>; reset-names = "host1x"; #address-cells = <1>; #size-cells = <1>; ranges = <0x54000000 0x54000000 0x04000000>; mpe { compatible = "nvidia,tegra20-mpe"; reg = <0x54040000 0x00040000>; interrupts = <0 68 0x04>; clocks = <&tegra_car TEGRA20_CLK_MPE>; resets = <&tegra_car 60>; reset-names = "mpe"; }; vi@54080000 { compatible = "nvidia,tegra210-vi"; reg = <0x0 0x54080000 0x0 0x700>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; clocks = <&tegra_car TEGRA210_CLK_VI>; power-domains = <&pd_venc>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x54080000 0x2000>; csi@838 { compatible = "nvidia,tegra210-csi"; reg = <0x838 0x1300>; assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, <&tegra_car TEGRA210_CLK_CILCD>, <&tegra_car TEGRA210_CLK_CILE>, <&tegra_car TEGRA210_CLK_CSI_TPG>; assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, <&tegra_car TEGRA210_CLK_PLL_P>, <&tegra_car TEGRA210_CLK_PLL_P>; assigned-clock-rates = <102000000>, <102000000>, <102000000>, <972000000>; clocks = <&tegra_car TEGRA210_CLK_CSI>, <&tegra_car TEGRA210_CLK_CILAB>, <&tegra_car TEGRA210_CLK_CILCD>, <&tegra_car TEGRA210_CLK_CILE>, <&tegra_car TEGRA210_CLK_CSI_TPG>; clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; power-domains = <&pd_sor>; }; }; epp { compatible = "nvidia,tegra20-epp"; reg = <0x540c0000 0x00040000>; interrupts = <0 70 0x04>; clocks = <&tegra_car TEGRA20_CLK_EPP>; resets = <&tegra_car 19>; reset-names = "epp"; }; isp { compatible = "nvidia,tegra20-isp"; reg = <0x54100000 0x00040000>; interrupts = <0 71 0x04>; clocks = <&tegra_car TEGRA20_CLK_ISP>; resets = <&tegra_car 23>; reset-names = "isp"; }; gr2d { compatible = "nvidia,tegra20-gr2d"; reg = <0x54140000 0x00040000>; interrupts = <0 72 0x04>; clocks = <&tegra_car TEGRA20_CLK_GR2D>; resets = <&tegra_car 21>; reset-names = "2d"; }; gr3d { compatible = "nvidia,tegra20-gr3d"; reg = <0x54180000 0x00040000>; clocks = <&tegra_car TEGRA20_CLK_GR3D>; resets = <&tegra_car 24>; reset-names = "3d"; }; dc@54200000 { compatible = "nvidia,tegra20-dc"; reg = <0x54200000 0x00040000>; interrupts = <0 73 0x04>; clocks = <&tegra_car TEGRA20_CLK_DISP1>, <&tegra_car TEGRA20_CLK_PLL_P>; clock-names = "dc", "parent"; resets = <&tegra_car 27>; reset-names = "dc"; rgb { status = "disabled"; }; }; dc@54240000 { compatible = "nvidia,tegra20-dc"; reg = <0x54240000 0x00040000>; interrupts = <0 74 0x04>; clocks = <&tegra_car TEGRA20_CLK_DISP2>, <&tegra_car TEGRA20_CLK_PLL_P>; clock-names = "dc", "parent"; resets = <&tegra_car 26>; reset-names = "dc"; rgb { status = "disabled"; }; }; hdmi { compatible = "nvidia,tegra20-hdmi"; reg = <0x54280000 0x00040000>; interrupts = <0 75 0x04>; clocks = <&tegra_car TEGRA20_CLK_HDMI>, <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; clock-names = "hdmi", "parent"; resets = <&tegra_car 51>; reset-names = "hdmi"; status = "disabled"; }; tvo { compatible = "nvidia,tegra20-tvo"; reg = <0x542c0000 0x00040000>; interrupts = <0 76 0x04>; clocks = <&tegra_car TEGRA20_CLK_TVO>; status = "disabled"; }; dsi { compatible = "nvidia,tegra20-dsi"; reg = <0x54300000 0x00040000>; clocks = <&tegra_car TEGRA20_CLK_DSI>, <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; clock-names = "dsi", "parent"; resets = <&tegra_car 48>; reset-names = "dsi"; status = "disabled"; }; }; ... };
Upload File
Create Folder