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usr / src / sys / contrib / device-tree / Bindings / reset /

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📄 allwinner,sun6i-a31-clock-reset.yaml(1.48 KB)
📄 amlogic,meson-axg-audio-arb.txt(669 B)
📄 amlogic,meson-reset.yaml(985 B)
📄 ath79-reset.txt(580 B)
📄 berlin,reset.txt(490 B)
📄 bitmain,bm1880-reset.txt(515 B)
📄 brcm,bcm63138-pmb.txt(608 B)
📄 brcm,bcm7216-pcie-sata-rescal.yaml(918 B)
📄 brcm,brcmstb-reset.txt(676 B)
📄 fsl,imx-src.txt(1.34 KB)
📄 fsl,imx-src.yaml(1.97 KB)
📄 fsl,imx7-src.txt(1.61 KB)
📄 fsl,imx7-src.yaml(1.34 KB)
📄 hisilicon,hi3660-reset.txt(1.33 KB)
📄 hisilicon,hi6220-reset.txt(1.1 KB)
📄 img,pistachio-reset.txt(1.64 KB)
📄 intel,rcu-gw.yaml(1.61 KB)
📄 lantiq,reset.txt(1.01 KB)
📄 nuvoton,npcm-reset.txt(961 B)
📄 nxp,lpc1850-rgu.txt(1.89 KB)
📄 oxnas,reset.txt(967 B)
📄 qcom,aoss-reset.yaml(1.05 KB)
📄 qcom,pdc-global.yaml(1.06 KB)
📄 renesas,rst.yaml(2.09 KB)
📄 reset.txt(2.9 KB)
📄 sirf,rstc.txt(1.25 KB)
📄 snps,axs10x-reset.txt(922 B)
📄 snps,dw-reset.txt(710 B)
📄 snps,hsdk-reset.txt(761 B)
📄 socfpga-reset.txt(488 B)
📄 socionext,uniphier-reset.yaml(3.05 KB)
📄 st,sti-picophyreset.txt(1.44 KB)
📄 st,sti-powerdown.txt(1.48 KB)
📄 st,sti-softreset.txt(1.37 KB)
📄 st,stm32-rcc.txt(227 B)
📄 st,stm32mp1-rcc.txt(237 B)
📄 ti,sci-reset.txt(2.24 KB)
📄 ti-syscon-reset.txt(3.11 KB)
📄 uniphier-reset.txt(1.86 KB)
📄 xlnx,zynqmp-reset.txt(1.25 KB)
📄 zte,zx2967-reset.txt(502 B)
📄 zynq-reset.txt(1.35 KB)

Editing: nxp,lpc1850-rgu.txt

NXP LPC1850  Reset Generation Unit (RGU)
========================================

Please also refer to reset.txt in this directory for common reset
controller binding usage.

Required properties:
- compatible: Should be "nxp,lpc1850-rgu"
- reg: register base and length
- clocks: phandle and clock specifier to RGU clocks
- clock-names: should contain "delay" and "reg"
- #reset-cells: should be 1

See table below for valid peripheral reset numbers. Numbers not
in the table below are either reserved or not applicable for
normal operation.

Reset	Peripheral
  9	System control unit (SCU)
 12	ARM Cortex-M0 subsystem core (LPC43xx only)
 13	CPU core
 16	LCD controller
 17	USB0
 18	USB1
 19	DMA
 20	SDIO
 21	External memory controller (EMC)
 22	Ethernet
 25	Flash bank A
 27	EEPROM
 28	GPIO
 29	Flash bank B
 32	Timer0
 33	Timer1
 34	Timer2
 35	Timer3
 36	Repetitive Interrupt timer (RIT)
 37	State Configurable Timer (SCT)
 38	Motor control PWM (MCPWM)
 39	QEI
 40	ADC0
 41	ADC1
 42	DAC
 44	USART0
 45	UART1
 46	USART2
 47	USART3
 48	I2C0
 49	I2C1
 50	SSP0
 51	SSP1
 52	I2S0 and I2S1
 53	Serial Flash Interface (SPIFI)
 54	C_CAN1
 55	C_CAN0
 56	ARM Cortex-M0 application core (LPC4370 only)
 57	SGPIO (LPC43xx only)
 58	SPI (LPC43xx only)
 60	ADCHS (12-bit ADC) (LPC4370 only)

Refer to NXP LPC18xx or LPC43xx user manual for more details about
the reset signals and the connected block/peripheral.

Reset provider example:
rgu: reset-controller@40053000 {
	compatible = "nxp,lpc1850-rgu";
	reg = <0x40053000 0x1000>;
	clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
	clock-names = "delay", "reg";
	#reset-cells = <1>;
};

Reset consumer example:
mac: ethernet@40010000 {
	compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
	reg = <0x40010000 0x2000>;
	interrupts = <5>;
	interrupt-names = "macirq";
	clocks = <&ccu1 CLK_CPU_ETHERNET>;
	clock-names = "stmmaceth";
	resets = <&rgu 22>;
	reset-names = "stmmaceth";
};

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Editing: nxp,lpc1850-rgu.txt

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