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_align.h
(87 B)
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_bus.h
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_inttypes.h
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_limits.h
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_stdint.h
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_types.h
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acpica_machdep.h
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apm_bios.h
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apm_segments.h
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asm.h
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asmacros.h
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atomic.h
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bootinfo.h
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bus.h
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bus_dma.h
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clock.h
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counter.h
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cpu.h
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cpufunc.h
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cputypes.h
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cserial.h
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db_machdep.h
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dump.h
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efi.h
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elan_mmcr.h
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elf.h
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endian.h
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exec.h
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fdt.h
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float.h
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floatingpoint.h
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fpu.h
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frame.h
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gdb_machdep.h
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ieeefp.h
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in_cksum.h
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intr_machdep.h
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iodev.h
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iommu.h
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kdb.h
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limits.h
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md_var.h
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memdev.h
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metadata.h
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minidump.h
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mp_watchdog.h
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nexusvar.h
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npx.h
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ofw_machdep.h
(92 B)
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param.h
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pc
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pcb.h
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pcb_ext.h
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pci_cfgreg.h
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pcpu.h
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pcpu_aux.h
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perfmon.h
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pmap.h
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pmap_base.h
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pmap_nopae.h
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pmap_pae.h
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pmc_mdep.h
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ppireg.h
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proc.h
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procctl.h
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profile.h
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psl.h
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ptrace.h
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pvclock.h
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reg.h
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reloc.h
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resource.h
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runq.h
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segments.h
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setjmp.h
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sf_buf.h
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sigframe.h
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signal.h
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smapi.h
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smp.h
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speaker.h
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specialreg.h
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stack.h
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stdarg.h
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sysarch.h
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timerreg.h
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trap.h
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tss.h
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ucontext.h
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vdso.h
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vm.h
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vm86.h
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vmparam.h
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xen
Editing: param.h
/*- * SPDX-License-Identifier: BSD-3-Clause * * Copyright (c) 1990 The Regents of the University of California. * All rights reserved. * * This code is derived from software contributed to Berkeley by * William Jolitz. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: @(#)param.h 5.8 (Berkeley) 6/28/91 * $FreeBSD$ */ #ifndef _I386_INCLUDE_PARAM_H_ #define _I386_INCLUDE_PARAM_H_ #include <machine/_align.h> /* * Machine dependent constants for Intel 386. */ #define __HAVE_ACPI #define __HAVE_PIR #define __PCI_REROUTE_INTERRUPT #ifndef MACHINE #define MACHINE "i386" #endif #ifndef MACHINE_ARCH #define MACHINE_ARCH "i386" #endif #define MID_MACHINE MID_I386 #ifdef SMP #ifndef MAXCPU #define MAXCPU 32 #endif #else #define MAXCPU 1 #endif #ifndef MAXMEMDOM #define MAXMEMDOM 1 #endif #define ALIGNBYTES _ALIGNBYTES #define ALIGN(p) _ALIGN(p) /* * ALIGNED_POINTER is a boolean macro that checks whether an address * is valid to fetch data elements of type t from on this architecture. * This does not reflect the optimal alignment, just the possibility * (within reasonable limits). */ #define ALIGNED_POINTER(p, t) 1 /* * CACHE_LINE_SIZE is the compile-time maximum cache line size for an * architecture. It should be used with appropriate caution. */ #define CACHE_LINE_SHIFT 6 #define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT) #define PAGE_SHIFT 12 /* LOG2(PAGE_SIZE) */ #define PAGE_SIZE (1 << PAGE_SHIFT) /* bytes/page */ #define PAGE_MASK (PAGE_SIZE - 1) #define NPTEPG (PAGE_SIZE / sizeof(pt_entry_t)) /* Size in bytes of the page directory */ #define NBPTD (NPGPTD << PAGE_SHIFT) /* Number of PDEs in page directory, 2048 for PAE, 1024 for non-PAE */ #define NPDEPTD (NBPTD / sizeof(pd_entry_t)) /* Number of PDEs in one page of the page directory, 512 vs. 1024 */ #define NPDEPG (PAGE_SIZE / sizeof(pd_entry_t)) #define PDRMASK (NBPDR - 1) #ifndef PDRSHIFT #define PDRSHIFT i386_pmap_PDRSHIFT #endif #ifndef NBPDR #define NBPDR (1 << PDRSHIFT) /* bytes/page dir */ #endif #define MAXPAGESIZES 2 /* maximum number of supported page sizes */ #define IOPAGES 2 /* pages of i/o permission bitmap */ #ifndef KSTACK_PAGES #define KSTACK_PAGES 4 /* Includes pcb! */ #endif #define KSTACK_GUARD_PAGES 1 /* pages of kstack guard; 0 disables */ #if KSTACK_PAGES < 4 #define TD0_KSTACK_PAGES 4 #else #define TD0_KSTACK_PAGES KSTACK_PAGES #endif /* * Ceiling on amount of swblock kva space, can be changed via * the kern.maxswzone /boot/loader.conf variable. * * 276 is sizeof(struct swblock), but we do not always have a definition * in scope for struct swblock, so we have to hardcode it. Each struct * swblock holds metadata for 32 pages, so in theory, this is enough for * 16 GB of swap. In practice, however, the usable amount is considerably * lower due to fragmentation. */ #ifndef VM_SWZONE_SIZE_MAX #define VM_SWZONE_SIZE_MAX (276 * 128 * 1024) #endif /* * Ceiling on size of buffer cache (really only effects write queueing, * the VM page cache is not effected), can be changed via * the kern.maxbcache /boot/loader.conf variable. * * The value is equal to the size of the auto-tuned buffer map for * the machine with 4GB of RAM, see vfs_bio.c:kern_vfs_bio_buffer_alloc(). */ #ifndef VM_BCACHE_SIZE_MAX #define VM_BCACHE_SIZE_MAX (7224 * 16 * 1024) #endif /* * Mach derived conversion macros */ #define trunc_page(x) ((x) & ~PAGE_MASK) #define round_page(x) (((x) + PAGE_MASK) & ~PAGE_MASK) #define trunc_4mpage(x) ((x) & ~PDRMASK) #define round_4mpage(x) ((((x)) + PDRMASK) & ~PDRMASK) #define atop(x) ((x) >> PAGE_SHIFT) #define ptoa(x) ((x) << PAGE_SHIFT) #define i386_btop(x) ((x) >> PAGE_SHIFT) #define i386_ptob(x) ((x) << PAGE_SHIFT) #define pgtok(x) ((x) * (PAGE_SIZE / 1024)) #define INKERNEL(va) (TRUE) #endif /* !_I386_INCLUDE_PARAM_H_ */
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