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📄 bcm_osal.h(19.56 KB)
📄 common_hsi.h(61.66 KB)
📄 ecore.h(27.87 KB)
📄 ecore_chain.h(22.8 KB)
📄 ecore_cxt.c(77.15 KB)
📄 ecore_cxt.h(6.75 KB)
📄 ecore_cxt_api.h(2.18 KB)
📄 ecore_dbg_fw_funcs.c(213.09 KB)
📄 ecore_dbg_fw_funcs.h(32.17 KB)
📄 ecore_dbg_values.h(600.82 KB)
📄 ecore_dcbx.c(54.45 KB)
📄 ecore_dcbx.h(2.99 KB)
📄 ecore_dcbx_api.h(7.84 KB)
📄 ecore_dev.c(200.72 KB)
📄 ecore_dev_api.h(22.83 KB)
📄 ecore_fcoe.h(2.54 KB)
📄 ecore_fcoe_api.h(4.17 KB)
📄 ecore_gtt_reg_addr.h(3.08 KB)
📄 ecore_gtt_values.h(2.06 KB)
📄 ecore_hsi_common.h(113.62 KB)
📄 ecore_hsi_debug_tools.h(31.34 KB)
📄 ecore_hsi_eth.h(162.39 KB)
📄 ecore_hsi_fcoe.h(77.08 KB)
📄 ecore_hsi_init_func.h(4.38 KB)
📄 ecore_hsi_init_tool.h(11.21 KB)
📄 ecore_hsi_iscsi.h(66.12 KB)
📄 ecore_hsi_iwarp.h(85.78 KB)
📄 ecore_hsi_rdma.h(109.48 KB)
📄 ecore_hsi_roce.h(152.46 KB)
📄 ecore_hw.c(34.16 KB)
📄 ecore_hw.h(7.51 KB)
📄 ecore_hw_defs.h(2.89 KB)
📄 ecore_init_fw_funcs.c(62.36 KB)
📄 ecore_init_fw_funcs.h(18.03 KB)
📄 ecore_init_ops.c(17.8 KB)
📄 ecore_init_ops.h(3.48 KB)
📄 ecore_init_values.h(3.82 MB)
📄 ecore_int.c(82.2 KB)
📄 ecore_int.h(7.81 KB)
📄 ecore_int_api.h(9.68 KB)
📄 ecore_iov_api.h(26.59 KB)
📄 ecore_iro.h(12.77 KB)
📄 ecore_iro_values.h(6.43 KB)
📄 ecore_iscsi.h(5.06 KB)
📄 ecore_iscsi_api.h(9.68 KB)
📄 ecore_iwarp.c(112.7 KB)
📄 ecore_iwarp.h(9.35 KB)
📄 ecore_l2.c(70.53 KB)
📄 ecore_l2.h(5.65 KB)
📄 ecore_l2_api.h(14.78 KB)
📄 ecore_ll2.c(64.13 KB)
📄 ecore_ll2.h(4.8 KB)
📄 ecore_ll2_api.h(9.31 KB)
📄 ecore_mcp.c(137.13 KB)
📄 ecore_mcp.h(18.21 KB)
📄 ecore_mcp_api.h(34.74 KB)
📄 ecore_mng_tlv.c(41.74 KB)
📄 ecore_ooo.c(17.19 KB)
📄 ecore_ooo.h(4.38 KB)
📄 ecore_proto_if.h(5.1 KB)
📄 ecore_rdma.c(77.63 KB)
📄 ecore_rdma.h(8.2 KB)
📄 ecore_rdma_api.h(27.11 KB)
📄 ecore_roce.c(44.5 KB)
📄 ecore_roce.h(3.15 KB)
📄 ecore_roce_api.h(24.77 KB)
📄 ecore_rt_defs.h(39.47 KB)
📄 ecore_sp_api.h(2.8 KB)
📄 ecore_sp_commands.c(21.81 KB)
📄 ecore_sp_commands.h(5.51 KB)
📄 ecore_spq.c(32.43 KB)
📄 ecore_spq.h(10.68 KB)
📄 ecore_sriov.c(138.24 KB)
📄 ecore_sriov.h(9.87 KB)
📄 ecore_status.h(1.9 KB)
📄 ecore_tcp_ip.h(3.38 KB)
📄 ecore_utils.h(2.46 KB)
📄 ecore_vf.c(55.16 KB)
📄 ecore_vf.h(13.59 KB)
📄 ecore_vf_api.h(7.97 KB)
📄 ecore_vfpf_if.h(17.38 KB)
📄 eth_common.h(24.37 KB)
📄 fcoe_common.h(55.08 KB)
📄 iscsi_common.h(95.1 KB)
📄 iwarp_common.h(2.48 KB)
📄 mcp_private.h(14.55 KB)
📄 mcp_public.h(87.13 KB)
📄 mfw_hsi.h(2.53 KB)
📄 nvm_cfg.h(135.26 KB)
📄 nvm_map.h(13.94 KB)
📄 pcics_reg_driver.h(26.05 KB)
📄 qlnx_def.h(21.3 KB)
📄 qlnx_ioctl.c(25.47 KB)
📄 qlnx_ioctl.h(8.41 KB)
📄 qlnx_os.c(225.04 KB)
📄 qlnx_os.h(3.96 KB)
📄 qlnx_rdma.c(7.21 KB)
📄 qlnx_rdma.h(2.37 KB)
📄 qlnx_ver.h(1.6 KB)
📄 rdma_common.h(41.19 KB)
📄 reg_addr.h(16.08 MB)
📄 roce_common.h(2.8 KB)
📄 spad_layout.h(10.2 KB)
📄 storage_common.h(7.43 KB)
📄 tcp_common.h(12.41 KB)

Editing: qlnx_ioctl.h

/*
 * Copyright (c) 2017-2018 Cavium, Inc. 
 * All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright
 *     notice, this list of conditions and the following disclaimer in the
 *     documentation and/or other materials provided with the distribution.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 *
 * $FreeBSD$
 *
 */

#ifndef _QLNX_IOCTL_H_
#define _QLNX_IOCTL_H_

#include <sys/ioccom.h>

#define QLNX_MAX_HW_FUNCS	2

/*
 * Read grcdump and grcdump size
 */

struct qlnx_grcdump {
	uint16_t	pci_func;
	uint32_t	grcdump_size[QLNX_MAX_HW_FUNCS];
	void		*grcdump[QLNX_MAX_HW_FUNCS];
	uint32_t	grcdump_dwords[QLNX_MAX_HW_FUNCS];
};
typedef struct qlnx_grcdump qlnx_grcdump_t;

/*
 * Read idle_chk and idle_chk size
 */
struct qlnx_idle_chk {
	uint16_t	pci_func;
	uint32_t	idle_chk_size[QLNX_MAX_HW_FUNCS];
	void		*idle_chk[QLNX_MAX_HW_FUNCS];
	uint32_t	idle_chk_dwords[QLNX_MAX_HW_FUNCS];
};
typedef struct qlnx_idle_chk qlnx_idle_chk_t;

/*
 * Retrive traces
 */
struct qlnx_trace {
	uint16_t	pci_func;

uint16_t	cmd;
#define QLNX_MCP_TRACE			0x01
#define QLNX_REG_FIFO			0x02
#define QLNX_IGU_FIFO			0x03
#define QLNX_PROTECTION_OVERRIDE	0x04
#define QLNX_FW_ASSERTS			0x05

uint32_t	size[QLNX_MAX_HW_FUNCS];
	void		*buffer[QLNX_MAX_HW_FUNCS];
	uint32_t	dwords[QLNX_MAX_HW_FUNCS];
};
typedef struct qlnx_trace qlnx_trace_t;

/*
 * Read driver info
 */
#define QLNX_DRV_INFO_NAME_LENGTH		32
#define QLNX_DRV_INFO_VERSION_LENGTH		32
#define QLNX_DRV_INFO_MFW_VERSION_LENGTH	32
#define QLNX_DRV_INFO_STORMFW_VERSION_LENGTH	32
#define QLNX_DRV_INFO_BUS_INFO_LENGTH		32

struct qlnx_drvinfo {
	char		drv_name[QLNX_DRV_INFO_NAME_LENGTH];
	char		drv_version[QLNX_DRV_INFO_VERSION_LENGTH];
	char		mfw_version[QLNX_DRV_INFO_MFW_VERSION_LENGTH];
	char		stormfw_version[QLNX_DRV_INFO_STORMFW_VERSION_LENGTH];
	uint32_t	eeprom_dump_len; /* in bytes */
	uint32_t	reg_dump_len; /* in bytes */
	char		bus_info[QLNX_DRV_INFO_BUS_INFO_LENGTH];
};
typedef struct qlnx_drvinfo qlnx_drvinfo_t;

/*
 * Read Device Setting
 */
struct qlnx_dev_setting {
	uint32_t	supported; /* Features this interface supports */
	uint32_t	advertising; /* Features this interface advertises */
	uint32_t	speed; /* The forced speed, 10Mb, 100Mb, gigabit */
	uint32_t	duplex; /* Duplex, half or full */
	uint32_t	port; /* Which connector port */
	uint32_t	phy_address; /* port number*/
	uint32_t	autoneg; /* Enable or disable autonegotiation */
};
typedef struct qlnx_dev_setting qlnx_dev_setting_t;

/*
 * Get Registers
 */
struct qlnx_get_regs {
	void		*reg_buf;
	uint32_t	reg_buf_len;
};
typedef struct qlnx_get_regs qlnx_get_regs_t;

/*
 * Get/Set NVRAM
 */
struct qlnx_nvram {
	uint32_t	cmd;
#define QLNX_NVRAM_CMD_WRITE_NVRAM	0x01
#define QLNX_NVRAM_CMD_READ_NVRAM	0x02
#define QLNX_NVRAM_CMD_SET_SECURE_MODE	0x03
#define QLNX_NVRAM_CMD_DEL_FILE		0x04
#define QLNX_NVRAM_CMD_PUT_FILE_BEGIN	0x05
#define QLNX_NVRAM_CMD_GET_NVRAM_RESP	0x06
#define QLNX_NVRAM_CMD_PUT_FILE_DATA	0x07

void		*data;
	uint32_t	offset;
	uint32_t	data_len;
	uint32_t	magic;
};
typedef struct qlnx_nvram qlnx_nvram_t;

/*
 * Get/Set Device registers
 */
struct qlnx_reg_rd_wr {
	uint32_t	cmd;
#define QLNX_REG_READ_CMD	0x01
#define QLNX_REG_WRITE_CMD	0x02

uint32_t	addr;
	uint32_t	val;

uint32_t	access_type;
#define QLNX_REG_ACCESS_DIRECT		0x01
#define QLNX_REG_ACCESS_INDIRECT	0x02

uint32_t	hwfn_index;
};
typedef struct qlnx_reg_rd_wr qlnx_reg_rd_wr_t;

/*
 * Read/Write PCI Configuration
 */
struct qlnx_pcicfg_rd_wr {
	uint32_t	cmd;
#define QLNX_PCICFG_READ		0x01
#define QLNX_PCICFG_WRITE		0x02
	uint32_t	reg;
	uint32_t	val;
	uint32_t	width;
};
typedef struct qlnx_pcicfg_rd_wr qlnx_pcicfg_rd_wr_t;

/*
 * Read MAC address
 */
struct qlnx_perm_mac_addr {
	char	addr[32];
};
typedef struct qlnx_perm_mac_addr qlnx_perm_mac_addr_t;

/*
 * Read STORM statistics registers
 */
struct qlnx_storm_stats {
	/* xstorm */
	uint32_t xstorm_active_cycles;
	uint32_t xstorm_stall_cycles;
	uint32_t xstorm_sleeping_cycles;
	uint32_t xstorm_inactive_cycles;

/* ystorm */
	uint32_t ystorm_active_cycles;
	uint32_t ystorm_stall_cycles;
	uint32_t ystorm_sleeping_cycles;
	uint32_t ystorm_inactive_cycles;

/* pstorm */
	uint32_t pstorm_active_cycles;
	uint32_t pstorm_stall_cycles;
	uint32_t pstorm_sleeping_cycles;
	uint32_t pstorm_inactive_cycles;

/* tstorm */
	uint32_t tstorm_active_cycles;
	uint32_t tstorm_stall_cycles;
	uint32_t tstorm_sleeping_cycles;
	uint32_t tstorm_inactive_cycles;

/* mstorm */
	uint32_t mstorm_active_cycles;
	uint32_t mstorm_stall_cycles;
	uint32_t mstorm_sleeping_cycles;
	uint32_t mstorm_inactive_cycles;

/* ustorm */
	uint32_t ustorm_active_cycles;
	uint32_t ustorm_stall_cycles;
	uint32_t ustorm_sleeping_cycles;
	uint32_t ustorm_inactive_cycles;
};

typedef struct qlnx_storm_stats qlnx_storm_stats_t;

#define QLNX_STORM_STATS_SAMPLES_PER_HWFN	(10000)

#define QLNX_STORM_STATS_BYTES_PER_HWFN (sizeof(qlnx_storm_stats_t) * \
		QLNX_STORM_STATS_SAMPLES_PER_HWFN)

struct qlnx_storm_stats_dump {
	int num_hwfns;
	int num_samples;
	void *buffer[QLNX_MAX_HW_FUNCS];
};

typedef struct qlnx_storm_stats_dump qlnx_storm_stats_dump_t;

#define QLNX_LLDP_TYPE_END_OF_LLDPDU		0
#define QLNX_LLDP_TYPE_CHASSIS_ID		1	
#define QLNX_LLDP_TYPE_PORT_ID			2	
#define QLNX_LLDP_TYPE_TTL			3
#define QLNX_LLDP_TYPE_PORT_DESC		4
#define QLNX_LLDP_TYPE_SYS_NAME			5
#define QLNX_LLDP_TYPE_SYS_DESC			6
#define QLNX_LLDP_TYPE_SYS_CAPS			7
#define QLNX_LLDP_TYPE_MGMT_ADDR		8
#define QLNX_LLDP_TYPE_ORG_SPECIFIC		127

#define QLNX_LLDP_CHASSIS_ID_SUBTYPE_OCTETS	1 //Subtype is 1 byte
#define QLNX_LLDP_CHASSIS_ID_SUBTYPE_MAC	0x04 //Mac Address
#define QLNX_LLDP_CHASSIS_ID_MAC_ADDR_LEN	6 // Mac address is 6 bytes
#define QLNX_LLDP_CHASSIS_ID_SUBTYPE_IF_NAME	0x06 //Interface Name

#define QLNX_LLDP_PORT_ID_SUBTYPE_OCTETS	1 //Subtype is 1 byte
#define QLNX_LLDP_PORT_ID_SUBTYPE_MAC		0x03 //Mac Address
#define QLNX_LLDP_PORT_ID_MAC_ADDR_LEN		6 // Mac address is 6 bytes
#define QLNX_LLDP_PORT_ID_SUBTYPE_IF_NAME	0x05 //Interface Name

#define QLNX_LLDP_SYS_TLV_SIZE 256
struct qlnx_lldp_sys_tlvs {
	int		discard_mandatory_tlv;
	uint8_t		buf[QLNX_LLDP_SYS_TLV_SIZE];
	uint16_t	buf_size;
};
typedef struct qlnx_lldp_sys_tlvs qlnx_lldp_sys_tlvs_t;

/*
 * Read grcdump size
 */
#define QLNX_GRC_DUMP_SIZE	_IOWR('q', 1, qlnx_grcdump_t)

/*
 * Read grcdump
 */
#define QLNX_GRC_DUMP		_IOWR('q', 2, qlnx_grcdump_t)

/*
 * Read idle_chk size
 */
#define QLNX_IDLE_CHK_SIZE	_IOWR('q', 3, qlnx_idle_chk_t)

/*
 * Read idle_chk
 */
#define QLNX_IDLE_CHK		_IOWR('q', 4, qlnx_idle_chk_t)

/*
 * Read driver info
 */
#define QLNX_DRV_INFO		_IOWR('q', 5, qlnx_drvinfo_t)

/*
 * Read Device Setting
 */
#define QLNX_DEV_SETTING	_IOR('q', 6, qlnx_dev_setting_t)

/*
 * Get Registers
 */
#define QLNX_GET_REGS		_IOR('q', 7, qlnx_get_regs_t)

/*
 * Get/Set NVRAM
 */
#define QLNX_NVRAM		_IOWR('q', 8, qlnx_nvram_t)

/*
 * Get/Set Device registers
 */
#define QLNX_RD_WR_REG		_IOWR('q', 9, qlnx_reg_rd_wr_t)

/*
 * Read/Write PCI Configuration
 */
#define QLNX_RD_WR_PCICFG	_IOWR('q', 10, qlnx_pcicfg_rd_wr_t)

/*
 * Read MAC address
 */
#define QLNX_MAC_ADDR		_IOWR('q', 11, qlnx_perm_mac_addr_t)

/*
 * Read STORM statistics
 */
#define QLNX_STORM_STATS	_IOWR('q', 12, qlnx_storm_stats_dump_t)

/*
 * Read trace size
 */
#define QLNX_TRACE_SIZE		_IOWR('q', 13, qlnx_trace_t)

/*
 * Read trace
 */
#define QLNX_TRACE		_IOWR('q', 14, qlnx_trace_t)

/*
 * Set LLDP TLVS
 */
#define QLNX_SET_LLDP_TLVS	_IOWR('q', 15, qlnx_lldp_sys_tlvs_t)

#endif /* #ifndef _QLNX_IOCTL_H_ */

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Editing: qlnx_ioctl.h

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