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rtd1293-ds418j.dts
(468 B)
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rtd1293.dtsi
(1.02 KB)
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rtd1295-mele-v9.dts
(426 B)
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rtd1295-probox2-ava.dts
(434 B)
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rtd1295-xnano-x5.dts
(451 B)
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rtd1295-zidoo-x9s.dts
(495 B)
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rtd1295.dtsi
(1.21 KB)
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rtd1296-ds418.dts
(466 B)
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rtd1296.dtsi
(1.21 KB)
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rtd129x.dtsi
(4.05 KB)
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rtd1395-bpi-m4.dts
(461 B)
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rtd1395-lionskin.dts
(550 B)
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rtd1395.dtsi
(1.21 KB)
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rtd139x.dtsi
(3.95 KB)
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rtd1619-mjolnir.dts
(688 B)
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rtd1619.dtsi
(212 B)
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rtd16xx.dtsi
(4.6 KB)
Editing: rtd1295.dtsi
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) /* * Realtek RTD1295 SoC * * Copyright (c) 2016-2019 Andreas FΓ€rber */ #include "rtd129x.dtsi" / { compatible = "realtek,rtd1295"; cpus { #address-cells = <2>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x0>; next-level-cache = <&l2>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x1>; next-level-cache = <&l2>; }; cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x2>; next-level-cache = <&l2>; }; cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x3>; next-level-cache = <&l2>; }; l2: l2-cache { compatible = "cache"; }; }; timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; }; &arm_pmu { interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; };
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