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📄 fsl-ls1012a-frdm.dts(1.77 KB)
📄 fsl-ls1012a-frwy.dts(619 B)
📄 fsl-ls1012a-oxalis.dts(1.61 KB)
📄 fsl-ls1012a-qds.dts(2.57 KB)
📄 fsl-ls1012a-rdb.dts(771 B)
📄 fsl-ls1012a.dtsi(13.52 KB)
📄 fsl-ls1028a-kontron-kbox-a-230-ls.dts(1.46 KB)
📄 fsl-ls1028a-kontron-sl28-var2.dts(1.34 KB)
📄 fsl-ls1028a-kontron-sl28-var3-ads2.dts(2.16 KB)
📄 fsl-ls1028a-kontron-sl28-var4.dts(1.05 KB)
📄 fsl-ls1028a-kontron-sl28.dts(2.9 KB)
📄 fsl-ls1028a-qds.dts(5.28 KB)
📄 fsl-ls1028a-rdb.dts(4.34 KB)
📄 fsl-ls1028a.dtsi(29.05 KB)
📄 fsl-ls1043-post.dtsi(780 B)
📄 fsl-ls1043a-qds.dts(2.41 KB)
📄 fsl-ls1043a-rdb.dts(3.65 KB)
📄 fsl-ls1043a.dtsi(22.32 KB)
📄 fsl-ls1046-post.dtsi(825 B)
📄 fsl-ls1046a-frwy.dts(2.51 KB)
📄 fsl-ls1046a-qds.dts(2.83 KB)
📄 fsl-ls1046a-rdb.dts(2.83 KB)
📄 fsl-ls1046a.dtsi(22.83 KB)
📄 fsl-ls1088a-qds.dts(2.61 KB)
📄 fsl-ls1088a-rdb.dts(1.82 KB)
📄 fsl-ls1088a.dtsi(22.01 KB)
📄 fsl-ls2080a-qds.dts(512 B)
📄 fsl-ls2080a-rdb.dts(507 B)
📄 fsl-ls2080a-simu.dts(542 B)
📄 fsl-ls2080a.dtsi(3.72 KB)
📄 fsl-ls2088a-qds.dts(458 B)
📄 fsl-ls2088a-rdb.dts(458 B)
📄 fsl-ls2088a.dtsi(3.61 KB)
📄 fsl-ls208xa-qds.dtsi(2.6 KB)
📄 fsl-ls208xa-rdb.dtsi(1.96 KB)
📄 fsl-ls208xa.dtsi(20.25 KB)
📄 fsl-lx2160a-cex7.dtsi(2.39 KB)
📄 fsl-lx2160a-clearfog-cx.dts(315 B)
📄 fsl-lx2160a-clearfog-itx.dtsi(692 B)
📄 fsl-lx2160a-honeycomb.dts(309 B)
📄 fsl-lx2160a-qds.dts(2.45 KB)
📄 fsl-lx2160a-rdb.dts(2.66 KB)
📄 fsl-lx2160a.dtsi(37.57 KB)
📄 imx8mm-beacon-baseboard.dtsi(6.28 KB)
📄 imx8mm-beacon-kit.dts(374 B)
📄 imx8mm-beacon-som.dtsi(9.83 KB)
📄 imx8mm-evk.dts(12.52 KB)
📄 imx8mm-pinfunc.h(63.02 KB)
📄 imx8mm.dtsi(27.25 KB)
📄 imx8mn-ddr4-evk.dts(3.12 KB)
📄 imx8mn-evk.dts(2.54 KB)
📄 imx8mn-evk.dtsi(8.1 KB)
📄 imx8mn-pinfunc.h(64.97 KB)
📄 imx8mn.dtsi(23.93 KB)
📄 imx8mp-evk.dts(6.75 KB)
📄 imx8mp-pinfunc.h(85.33 KB)
📄 imx8mp.dtsi(19.92 KB)
📄 imx8mq-evk.dts(11.98 KB)
📄 imx8mq-hummingboard-pulse.dts(5.94 KB)
📄 imx8mq-librem5-devkit.dts(21.7 KB)
📄 imx8mq-nitrogen.dts(10.51 KB)
📄 imx8mq-phanbell.dts(10.84 KB)
📄 imx8mq-pico-pi.dts(9.96 KB)
📄 imx8mq-pinfunc.h(60.77 KB)
📄 imx8mq-sr-som.dtsi(7.5 KB)
📄 imx8mq-thor96.dts(12.86 KB)
📄 imx8mq-zii-ultra-rmb3.dts(1.72 KB)
📄 imx8mq-zii-ultra-zest.dts(473 B)
📄 imx8mq-zii-ultra.dtsi(16.29 KB)
📄 imx8mq.dtsi(36.02 KB)
📄 imx8qxp-ai_ml.dts(5.86 KB)
📄 imx8qxp-colibri-eval-v3.dts(333 B)
📄 imx8qxp-colibri-eval-v3.dtsi(895 B)
📄 imx8qxp-colibri.dtsi(18.2 KB)
📄 imx8qxp-mek.dts(5.97 KB)
📄 imx8qxp.dtsi(16.6 KB)
📄 qoriq-bman-portals.dtsi(1.87 KB)
📄 qoriq-fman3-0-10g-0.dtsi(845 B)
📄 qoriq-fman3-0-10g-1.dtsi(845 B)
📄 qoriq-fman3-0-1g-0.dtsi(828 B)
📄 qoriq-fman3-0-1g-1.dtsi(828 B)
📄 qoriq-fman3-0-1g-2.dtsi(828 B)
📄 qoriq-fman3-0-1g-3.dtsi(828 B)
📄 qoriq-fman3-0-1g-4.dtsi(828 B)
📄 qoriq-fman3-0-1g-5.dtsi(828 B)
📄 qoriq-fman3-0.dtsi(1.8 KB)
📄 qoriq-qman-portals.dtsi(2.16 KB)
📄 s32v234-evb.dts(371 B)
📄 s32v234.dtsi(3.13 KB)

Editing: s32v234.dtsi

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2015-2016 Freescale Semiconductor, Inc.
 * Copyright 2016-2018 NXP
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/memreserve/ 0x80000000 0x00010000;

/ {
	compatible = "fsl,s32v234";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

cpus {
		#address-cells = <2>;
		#size-cells = <0>;

cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x0>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x80000000>;
			next-level-cache = <&cluster0_l2_cache>;
		};

cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x1>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x80000000>;
			next-level-cache = <&cluster0_l2_cache>;
		};

cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x100>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x80000000>;
			next-level-cache = <&cluster1_l2_cache>;
		};

cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x101>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x80000000>;
			next-level-cache = <&cluster1_l2_cache>;
		};

cluster0_l2_cache: l2-cache0 {
			compatible = "cache";
		};

cluster1_l2_cache: l2-cache1 {
			compatible = "cache";
		};
	};

timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
					  IRQ_TYPE_LEVEL_LOW)>;
		/* clock-frequency might be modified by u-boot, depending on the
		 * chip version.
		 */
		clock-frequency = <10000000>;
	};

gic: interrupt-controller@7d001000 {
		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0 0x7d001000 0 0x1000>,
		      <0 0x7d002000 0 0x2000>,
		      <0 0x7d004000 0 0x2000>,
		      <0 0x7d006000 0 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
					 IRQ_TYPE_LEVEL_HIGH)>;
	};

soc {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		ranges;

aips0: bus@40000000 {
			compatible = "simple-bus";
			#address-cells = <2>;
			#size-cells = <2>;
			interrupt-parent = <&gic>;
			reg = <0x0 0x40000000 0x0 0x7d000>;
			ranges;

uart0: serial@40053000 {
				compatible = "fsl,s32v234-linflexuart";
				reg = <0x0 0x40053000 0x0 0x1000>;
				interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
			};
		};

aips1: bus@40080000 {
			compatible = "simple-bus";
			#address-cells = <2>;
			#size-cells = <2>;
			interrupt-parent = <&gic>;
			reg = <0x0 0x40080000 0x0 0x70000>;
			ranges;

uart1: serial@400bc000 {
				compatible = "fsl,s32v234-linflexuart";
				reg = <0x0 0x400bc000 0x0 0x1000>;
				interrupts = <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
			};
		};
	};
};

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Editing: s32v234.dtsi

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