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📄 brcm,bcm6345-l1-intc.txt(1.92 KB)
📄 brcm,bcm7038-l1-intc.txt(2.13 KB)
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📄 faraday,ftintc010.txt(838 B)
📄 fsl,intmux.yaml(1.43 KB)
📄 fsl,irqsteer.yaml(2.16 KB)
📄 fsl,ls-extirq.txt(1.61 KB)
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📄 ingenic,intc.yaml(1.33 KB)
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📄 interrupts.txt(3.76 KB)
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📄 loongson,pch-msi.yaml(1.41 KB)
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📄 lsi,zevio-intc.txt(424 B)
📄 marvell,armada-370-xp-mpic.txt(1.47 KB)
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📄 marvell,orion-intc.txt(1.55 KB)
📄 marvell,sei.txt(1.33 KB)
📄 mediatek,cirq.txt(1.32 KB)
📄 mediatek,sysirq.txt(1.93 KB)
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📄 mrvl,intc.txt(2.35 KB)
📄 mrvl,intc.yaml(2.81 KB)
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📄 nvidia,tegra20-ictlr.txt(1.42 KB)
📄 nxp,lpc3220-mic.txt(1.7 KB)
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📄 qca,ath79-cpu-intc.txt(1.35 KB)
📄 qca,ath79-misc-intc.txt(1.3 KB)
📄 qcom,pdc.txt(2.36 KB)
📄 rda,8810pl-intc.txt(1.04 KB)
📄 renesas,h8300h-intc.txt(608 B)
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📄 renesas,intc-irqpin.yaml(2.86 KB)
📄 renesas,irqc.yaml(2.5 KB)
📄 renesas,rza1-irqc.txt(1.51 KB)
📄 renesas,rza1-irqc.yaml(2.14 KB)
📄 riscv,cpu-intc.txt(2.43 KB)
📄 samsung,exynos4210-combiner.txt(2.17 KB)
📄 samsung,s3c24xx-irq.txt(1.62 KB)
📄 sifive,plic-1.0.0.txt(2.59 KB)
📄 sigma,smp8642-intc.txt(1.26 KB)
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📄 snps,archs-idu-intc.txt(1.46 KB)
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📄 snps,dw-apb-ictl.txt(1.13 KB)
📄 socionext,synquacer-exiu.txt(1.05 KB)
📄 socionext,uniphier-aidet.yaml(1.6 KB)
📄 st,spear3xx-shirq.txt(1.81 KB)
📄 st,sti-irq-syscfg.txt(1.25 KB)
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📄 technologic,ts4800.txt(605 B)
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📄 ti,cp-intc.txt(844 B)
📄 ti,keystone-irq.txt(1.24 KB)
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📄 ti,omap2-intc.txt(809 B)
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📄 ti,sci-inta.txt(3.09 KB)
📄 ti,sci-inta.yaml(3.44 KB)
📄 ti,sci-intr.txt(3.44 KB)
📄 ti,sci-intr.yaml(3.59 KB)
📄 via,vt8500-intc.txt(417 B)

Editing: samsung,s3c24xx-irq.txt

Samsung S3C24XX Interrupt Controllers

The S3C24XX SoCs contain a custom set of interrupt controllers providing a
varying number of interrupt sources. The set consists of a main- and sub-
controller and on newer SoCs even a second main controller.

Required properties:
- compatible: Compatible property value should be "samsung,s3c2410-irq"
  for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later.

- reg: Physical base address of the controller and length of memory mapped
  region.

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an
  interrupt source. The value shall be 4 and interrupt descriptor shall
  have the following format:
      <ctrl_num parent_irq ctrl_irq type>

ctrl_num contains the controller to use:
      - 0 ... main controller
      - 1 ... sub controller
      - 2 ... second main controller on s3c2416 and s3c2450
  parent_irq contains the parent bit in the main controller and will be
             ignored in main controllers
  ctrl_irq contains the interrupt bit of the controller
  type contains the trigger type to use

Example:

interrupt-controller@4a000000 {
		compatible = "samsung,s3c2410-irq";
		reg = <0x4a000000 0x100>;
		interrupt-controller;
		#interrupt-cells=<4>;
	};

[...]

serial@50000000 {
		compatible = "samsung,s3c2410-uart";
		reg = <0x50000000 0x4000>;
		interrupt-parent = <&subintc>;
		interrupts = <1 28 0 4>, <1 28 1 4>;
	};

rtc@57000000 {
		compatible = "samsung,s3c2410-rtc";
		reg = <0x57000000 0x100>;
		interrupt-parent = <&intc>;
		interrupts = <0 30 0 3>, <0 8 0 3>;
	};

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Editing: samsung,s3c24xx-irq.txt

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