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📄 a3m071.dts(2.4 KB)
📄 a4m072.dts(3.03 KB)
📄 ac14xx.dts(7.71 KB)
📄 acadia.dts(5.06 KB)
📄 adder875-redboot.dts(3.72 KB)
📄 adder875-uboot.dts(3.69 KB)
📄 akebono.dts(12.21 KB)
📄 amigaone.dts(3.87 KB)
📄 arches.dts(8.41 KB)
📄 asp834x-redboot.dts(6.52 KB)
📄 bamboo.dts(7.75 KB)
📄 bluestone.dts(9.66 KB)
📄 canyonlands.dts(15.39 KB)
📄 charon.dts(5.01 KB)
📄 cm5200.dts(1.31 KB)
📄 currituck.dts(7.28 KB)
📄 digsy_mtc.dts(2.84 KB)
📄 ebony.dts(8.22 KB)
📄 eiger.dts(10.5 KB)
📄 ep8248e.dts(4.36 KB)
📄 ep88xc.dts(4.4 KB)
📁 fsl
📄 fsp2.dts(12.79 KB)
📄 gamecube.dts(2.2 KB)
📄 glacier.dts(15.87 KB)
📄 haleakala.dts(7.41 KB)
📄 holly.dts(4.8 KB)
📄 hotfoot.dts(7 KB)
📄 icon.dts(12.33 KB)
📄 iss4xx-mpic.dts(3.75 KB)
📄 iss4xx.dts(2.79 KB)
📄 katmai.dts(14.24 KB)
📄 kilauea.dts(11.5 KB)
📄 klondike.dts(4.88 KB)
📄 kmeter1.dts(13.19 KB)
📄 ksi8560.dts(7.59 KB)
📄 kuroboxHD.dts(3.67 KB)
📄 kuroboxHG.dts(3.68 KB)
📄 lite5200.dts(6.53 KB)
📄 lite5200b.dts(3.11 KB)
📄 makalu.dts(9.8 KB)
📄 media5200.dts(3.15 KB)
📄 mgcoge.dts(5.76 KB)
📄 motionpro.dts(2.41 KB)
📄 mpc5121.dtsi(11.75 KB)
📄 mpc5121ads.dts(3.38 KB)
📄 mpc5125twr.dts(6.55 KB)
📄 mpc5200b.dtsi(7.14 KB)
📄 mpc7448hpc2.dts(4.19 KB)
📄 mpc8272ads.dts(6.2 KB)
📄 mpc8308_p1m.dts(6.94 KB)
📄 mpc8308rdb.dts(6.49 KB)
📄 mpc8313erdb.dts(9.09 KB)
📄 mpc8315erdb.dts(10.71 KB)
📄 mpc832x_mds.dts(10.5 KB)
📄 mpc832x_rdb.dts(8.51 KB)
📄 mpc8349emitx.dts(9.31 KB)
📄 mpc8349emitxgp.dts(5.49 KB)
📄 mpc834x_mds.dts(9.53 KB)
📄 mpc836x_mds.dts(11.38 KB)
📄 mpc836x_rdk.dts(10.35 KB)
📄 mpc8377_mds.dts(11.28 KB)
📄 mpc8377_rdb.dts(11.12 KB)
📄 mpc8377_wlan.dts(10.24 KB)
📄 mpc8378_mds.dts(10.91 KB)
📄 mpc8378_rdb.dts(10.75 KB)
📄 mpc8379_mds.dts(9.98 KB)
📄 mpc8379_rdb.dts(9.83 KB)
📄 mpc8610_hpcd.dts(11.01 KB)
📄 mpc866ads.dts(3.92 KB)
📄 mpc885ads.dts(5.09 KB)
📄 mucmc52.dts(4.58 KB)
📄 mvme5100.dts(4.35 KB)
📄 o2d.dts(783 B)
📄 o2d.dtsi(2.08 KB)
📄 o2d300.dts(932 B)
📄 o2dnt2.dts(796 B)
📄 o2i.dts(505 B)
📄 o2mnt.dts(517 B)
📄 o3dnt.dts(791 B)
📄 obs600.dts(7.85 KB)
📄 pcm030.dts(2.19 KB)
📄 pcm032.dts(3.64 KB)
📄 pdm360ng.dts(3.39 KB)
📄 pq2fads.dts(5.69 KB)
📄 ps3.dts(1.25 KB)
📄 rainier.dts(8.83 KB)
📄 redwood.dts(10.7 KB)
📄 sam440ep.dts(7.24 KB)
📄 sbc8548-altflash.dts(2.3 KB)
📄 sbc8548-post.dtsi(6.82 KB)
📄 sbc8548-pre.dtsi(903 B)
📄 sbc8548.dts(2.17 KB)
📄 sequoia.dts(10.42 KB)
📄 socrates.dts(7.3 KB)
📄 storcenter.dts(3.12 KB)
📄 stx_gp3_8560.dts(6.41 KB)
📄 stxssa8555.dts(8.66 KB)
📄 taishan.dts(10.58 KB)
📄 tqm5200.dts(4.47 KB)
📄 tqm8540.dts(7.23 KB)
📄 tqm8541.dts(6.9 KB)
📄 tqm8548-bigflash.dts(10.95 KB)
📄 tqm8548.dts(10.95 KB)
📄 tqm8555.dts(6.9 KB)
📄 tqm8560.dts(8.58 KB)
📄 tqm8xx.dts(4 KB)
📄 uc101.dts(2.55 KB)
📄 warp.dts(7.03 KB)
📄 wii.dts(5.56 KB)
📄 xcalibur1501.dts(15.41 KB)
📄 xpedite5200.dts(9.96 KB)
📄 xpedite5200_xmon.dts(10.97 KB)
📄 xpedite5301.dts(14.24 KB)
📄 xpedite5330.dts(15.53 KB)
📄 xpedite5370.dts(14.16 KB)
📄 yosemite.dts(8.22 KB)

Editing: sbc8548-post.dtsi

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * SBC8548 Device Tree Source
 *
 * Copyright 2007 Wind River Systems Inc.
 *
 * Paul Gortmaker (see MAINTAINERS for contact information)
 */

/{
	soc8548@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		ranges = <0x00000000 0xe0000000 0x00100000>;
		bus-frequency = <0>;
		compatible = "simple-bus";

ecm-law@0 {
			compatible = "fsl,ecm-law";
			reg = <0x0 0x1000>;
			fsl,num-laws = <10>;
		};

ecm@1000 {
			compatible = "fsl,mpc8548-ecm", "fsl,ecm";
			reg = <0x1000 0x1000>;
			interrupts = <17 2>;
			interrupt-parent = <&mpic>;
		};

memory-controller@2000 {
			compatible = "fsl,mpc8548-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <0x12 0x2>;
		};

L2: l2-cache-controller@20000 {
			compatible = "fsl,mpc8548-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <0x20>;	// 32 bytes
			cache-size = <0x80000>;	// L2, 512K
			interrupt-parent = <&mpic>;
			interrupts = <0x10 0x2>;
		};

i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <0x2b 0x2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <0x2b 0x2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

enet0: ethernet@24000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			ranges = <0x0 0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi0>;
			phy-handle = <&phy0>;

mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-mdio";
				reg = <0x520 0x20>;

phy0: ethernet-phy@19 {
					interrupt-parent = <&mpic>;
					interrupts = <0x6 0x1>;
					reg = <0x19>;
				};
				phy1: ethernet-phy@1a {
					interrupt-parent = <&mpic>;
					interrupts = <0x7 0x1>;
					reg = <0x1a>;
				};
				tbi0: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

enet1: ethernet@25000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			ranges = <0x0 0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi1>;
			phy-handle = <&phy1>;

mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

tbi1: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4500 0x100>;	// reg base, size
			clock-frequency = <0>;	// should we fill in in uboot?
			interrupts = <0x2a 0x2>;
			interrupt-parent = <&mpic>;
		};

serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4600 0x100>;	// reg base, size
			clock-frequency = <0>;	// should we fill in in uboot?
			interrupts = <0x2a 0x2>;
			interrupt-parent = <&mpic>;
		};

global-utilities@e0000 {	//global utilities reg
			compatible = "fsl,mpc8548-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};

crypto@30000 {
			compatible = "fsl,sec2.1", "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <45 2>;
			interrupt-parent = <&mpic>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0xfe>;
			fsl,descriptor-types-mask = <0x12b0ebf>;
		};

mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};
	};

pci0: pci@e0008000 {
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
			/* IDSEL 0x01 (PCI-X slot) @66MHz */
			0x0800 0x0 0x0 0x1 &mpic 0x2 0x1
			0x0800 0x0 0x0 0x2 &mpic 0x3 0x1
			0x0800 0x0 0x0 0x3 &mpic 0x4 0x1
			0x0800 0x0 0x0 0x4 &mpic 0x1 0x1

/* IDSEL 0x11 (PCI, 3.3V 32bit) @33MHz */
			0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8800 0x0 0x0 0x4 &mpic 0x1 0x1>;

interrupt-parent = <&mpic>;
		interrupts = <0x18 0x2>;
		bus-range = <0 0>;
		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>;
		clock-frequency = <66000000>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008000 0x1000>;
		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
		device_type = "pci";
	};

pci1: pcie@e000a000 {
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

/* IDSEL 0x0 (PEX) */
			0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x0000 0x0 0x0 0x4 &mpic 0x3 0x1>;

interrupt-parent = <&mpic>;
		interrupts = <0x1a 0x2>;
		bus-range = <0x0 0xff>;
		ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
			  0x01000000 0x0 0x00000000 0xe2800000 0x0 0x08000000>;
		clock-frequency = <33000000>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe000a000 0x1000>;
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x02000000 0x0 0xa0000000
				  0x02000000 0x0 0xa0000000
				  0x0 0x10000000

0x01000000 0x0 0x00000000
				  0x01000000 0x0 0x00000000
				  0x0 0x00800000>;
		};
	};
};

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Editing: sbc8548-post.dtsi

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