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📄 intel_ata.h(25.31 KB)
📄 intel_pci.h(3.08 KB)
📄 intel_sas.h(30.43 KB)
📄 intel_sat.h(3.79 KB)
📄 intel_sata.h(8.02 KB)
📄 intel_scsi.h(20.25 KB)
📄 sati.c(39.3 KB)
📄 sati.h(10.92 KB)
📄 sati_abort_task_set.c(6.05 KB)
📄 sati_abort_task_set.h(3.27 KB)
📄 sati_atapi.c(8.5 KB)
📄 sati_atapi.h(7.71 KB)
📄 sati_callbacks.h(16.32 KB)
📄 sati_design.h(7.36 KB)
📄 sati_device.c(8.93 KB)
📄 sati_device.h(6.68 KB)
📄 sati_inquiry.c(27.11 KB)
📄 sati_inquiry.h(4.15 KB)
📄 sati_log_sense.c(24.41 KB)
📄 sati_log_sense.h(3.44 KB)
📄 sati_lun_reset.c(4.82 KB)
📄 sati_lun_reset.h(3.16 KB)
📄 sati_mode_pages.c(9.41 KB)
📄 sati_mode_pages.h(4.89 KB)
📄 sati_mode_select.c(37.17 KB)
📄 sati_mode_select.h(3.29 KB)
📄 sati_mode_sense.c(29.7 KB)
📄 sati_mode_sense.h(5.1 KB)
📄 sati_mode_sense_10.c(19.27 KB)
📄 sati_mode_sense_10.h(4.23 KB)
📄 sati_mode_sense_6.c(15.91 KB)
📄 sati_mode_sense_6.h(4.22 KB)
📄 sati_move.c(22.63 KB)
📄 sati_move.h(4.43 KB)
📄 sati_passthrough.c(17.55 KB)
📄 sati_passthrough.h(3.36 KB)
📄 sati_read.c(11.59 KB)
📄 sati_read.h(3.45 KB)
📄 sati_read_buffer.c(8.13 KB)
📄 sati_read_buffer.h(3.15 KB)
📄 sati_read_capacity.c(13.36 KB)
📄 sati_read_capacity.h(3.55 KB)
📄 sati_reassign_blocks.c(21.91 KB)
📄 sati_reassign_blocks.h(3.12 KB)
📄 sati_report_luns.c(5.04 KB)
📄 sati_report_luns.h(3.11 KB)
📄 sati_request_sense.c(12.11 KB)
📄 sati_request_sense.h(3.41 KB)
📄 sati_start_stop_unit.c(14.45 KB)
📄 sati_start_stop_unit.h(4.2 KB)
📄 sati_synchronize_cache.c(4.66 KB)
📄 sati_synchronize_cache.h(2.94 KB)
📄 sati_test_unit_ready.c(6.63 KB)
📄 sati_test_unit_ready.h(3.18 KB)
📄 sati_translator_sequence.h(10.92 KB)
📄 sati_types.h(5.14 KB)
📄 sati_unmap.c(22.99 KB)
📄 sati_unmap.h(4.66 KB)
📄 sati_util.c(72.2 KB)
📄 sati_util.h(13.53 KB)
📄 sati_verify.c(10.08 KB)
📄 sati_verify.h(3.23 KB)
📄 sati_write.c(11.64 KB)
📄 sati_write.h(3.45 KB)
📄 sati_write_and_verify.c(8.64 KB)
📄 sati_write_and_verify.h(3.45 KB)
📄 sati_write_buffer.c(8.94 KB)
📄 sati_write_buffer.h(3.06 KB)
📄 sati_write_long.c(8.25 KB)
📄 sati_write_long.h(3.2 KB)
📄 sci_abstract_list.c(15.87 KB)
📄 sci_abstract_list.h(36.67 KB)
📄 sci_base_controller.c(4.18 KB)
📄 sci_base_controller.h(11.67 KB)
📄 sci_base_domain.c(3.36 KB)
📄 sci_base_domain.h(9.88 KB)
📄 sci_base_iterator.c(5.56 KB)
📄 sci_base_iterator.h(4.34 KB)
📄 sci_base_library.c(3.71 KB)
📄 sci_base_library.h(6.19 KB)
📄 sci_base_logger.c(9.68 KB)
📄 sci_base_logger.h(4.12 KB)
📄 sci_base_memory_descriptor_list.c(5.99 KB)
📄 sci_base_memory_descriptor_list.h(5.97 KB)
📄 sci_base_memory_descriptor_list_decorator.c(5.42 KB)
📄 sci_base_object.c(4.06 KB)
📄 sci_base_object.h(4.74 KB)
📄 sci_base_observer.c(3.79 KB)
📄 sci_base_observer.h(5.39 KB)
📄 sci_base_phy.c(3.32 KB)
📄 sci_base_phy.h(6.67 KB)
📄 sci_base_port.c(3.29 KB)
📄 sci_base_port.h(7.1 KB)
📄 sci_base_remote_device.c(3 KB)
📄 sci_base_remote_device.h(9.65 KB)
📄 sci_base_request.c(2.98 KB)
📄 sci_base_request.h(6.48 KB)
📄 sci_base_state.h(3.6 KB)
📄 sci_base_state_machine.c(7.36 KB)
📄 sci_base_state_machine.h(5.04 KB)
📄 sci_base_state_machine_logger.c(8.77 KB)
📄 sci_base_state_machine_logger.h(5.47 KB)
📄 sci_base_state_machine_observer.c(3.81 KB)
📄 sci_base_state_machine_observer.h(4.67 KB)
📄 sci_base_subject.c(4.91 KB)
📄 sci_base_subject.h(4.8 KB)
📄 sci_controller.h(4.38 KB)
📄 sci_controller_constants.h(7.19 KB)
📄 sci_fast_list.h(11.91 KB)
📄 sci_iterator.h(4.23 KB)
📄 sci_library.h(3.71 KB)
📄 sci_logger.h(9.93 KB)
📄 sci_memory_descriptor_list.h(6.25 KB)
📄 sci_memory_descriptor_list_decorator.h(5.28 KB)
📄 sci_object.h(5.19 KB)
📄 sci_overview.h(10.95 KB)
📄 sci_pool.h(6.18 KB)
📄 sci_simple_list.h(11.04 KB)
📄 sci_status.h(14.61 KB)
📄 sci_types.h(8.59 KB)
📄 sci_util.c(2.72 KB)
📄 sci_util.h(5.54 KB)
📄 scic_config_parameters.h(11.02 KB)
📄 scic_controller.h(35.07 KB)
📄 scic_io_request.h(27 KB)
📄 scic_library.h(9.29 KB)
📄 scic_logger.h(5.26 KB)
📄 scic_overview.h(3.58 KB)
📄 scic_phy.h(15.08 KB)
📄 scic_port.h(8.01 KB)
📄 scic_remote_device.h(16.95 KB)
📄 scic_sds_controller.c(219.91 KB)
📄 scic_sds_controller.h(25.17 KB)
📄 scic_sds_controller_registers.h(15.37 KB)
📄 scic_sds_library.c(8.78 KB)
📄 scic_sds_library.h(3.81 KB)
📄 scic_sds_logger.h(3.33 KB)
📄 scic_sds_pci.c(8.47 KB)
📄 scic_sds_pci.h(4.64 KB)
📄 scic_sds_phy.c(120.86 KB)
📄 scic_sds_phy.h(14.08 KB)
📄 scic_sds_phy_registers.h(9.56 KB)
📄 scic_sds_port.c(104.9 KB)
📄 scic_sds_port.h(16.3 KB)
📄 scic_sds_port_configuration_agent.c(38.16 KB)
📄 scic_sds_port_configuration_agent.h(4.26 KB)
📄 scic_sds_port_registers.h(4.69 KB)
📄 scic_sds_remote_device.c(85.08 KB)
📄 scic_sds_remote_device.h(20.58 KB)
📄 scic_sds_remote_node_context.c(45.54 KB)
📄 scic_sds_remote_node_context.h(12.77 KB)
📄 scic_sds_remote_node_table.c(22.19 KB)
📄 scic_sds_remote_node_table.h(6.63 KB)
📄 scic_sds_request.c(88.54 KB)
📄 scic_sds_request.h(16.53 KB)
📄 scic_sds_sgpio.c(8.43 KB)
📄 scic_sds_smp_remote_device.c(12.13 KB)
📄 scic_sds_smp_request.c(29.64 KB)
📄 scic_sds_smp_request.h(3.01 KB)
📄 scic_sds_ssp_request.c(11.96 KB)
📄 scic_sds_stp_packet_request.c(32.87 KB)
📄 scic_sds_stp_packet_request.h(6.06 KB)
📄 scic_sds_stp_pio_request.h(4.49 KB)
📄 scic_sds_stp_remote_device.c(35.79 KB)
📄 scic_sds_stp_request.c(80.59 KB)
📄 scic_sds_stp_request.h(8.91 KB)
📄 scic_sds_unsolicited_frame_control.c(14.8 KB)
📄 scic_sds_unsolicited_frame_control.h(9.62 KB)
📄 scic_sgpio.h(9.79 KB)
📄 scic_task_request.h(7.41 KB)
📄 scic_user_callback.h(41.37 KB)
📄 scif_config_parameters.h(6.19 KB)
📄 scif_controller.h(17.94 KB)
📄 scif_domain.h(7.18 KB)
📄 scif_io_request.h(10.26 KB)
📄 scif_library.h(6.96 KB)
📄 scif_logger.h(4.54 KB)
📄 scif_overview.h(5.27 KB)
📄 scif_remote_device.h(12.12 KB)
📄 scif_sas_constants.h(2.97 KB)
📄 scif_sas_controller.c(39.23 KB)
📄 scif_sas_controller.h(9.32 KB)
📄 scif_sas_controller_state_handlers.c(66.96 KB)
📄 scif_sas_controller_states.c(13.31 KB)
📄 scif_sas_design.h(15.75 KB)
📄 scif_sas_domain.c(49.41 KB)
📄 scif_sas_domain.h(9.6 KB)
📄 scif_sas_domain_state_handlers.c(58.4 KB)
📄 scif_sas_domain_states.c(20.18 KB)
📄 scif_sas_high_priority_request_queue.c(5.86 KB)
📄 scif_sas_high_priority_request_queue.h(4.5 KB)
📄 scif_sas_internal_io_request.c(9.31 KB)
📄 scif_sas_internal_io_request.h(5.11 KB)
📄 scif_sas_io_request.c(27.08 KB)
📄 scif_sas_io_request.h(5.08 KB)
📄 scif_sas_io_request_state_handlers.c(13.93 KB)
📄 scif_sas_io_request_states.c(8.65 KB)
📄 scif_sas_library.c(8.96 KB)
📄 scif_sas_library.h(3.54 KB)
📄 scif_sas_logger.h(3.33 KB)
📄 scif_sas_remote_device.c(26.69 KB)
📄 scif_sas_remote_device.h(16.3 KB)
📄 scif_sas_remote_device_ready_substate_handlers.c(28.59 KB)
📄 scif_sas_remote_device_ready_substates.c(9.95 KB)
📄 scif_sas_remote_device_starting_substate_handlers.c(11.85 KB)
📄 scif_sas_remote_device_starting_substates.c(5.1 KB)
📄 scif_sas_remote_device_state_handlers.c(43.12 KB)
📄 scif_sas_remote_device_states.c(17.46 KB)
📄 scif_sas_request.c(6.87 KB)
📄 scif_sas_request.h(6.91 KB)
📄 scif_sas_sati_binding.h(11.21 KB)
📄 scif_sas_smp_activity_clear_affiliation.c(8.52 KB)
📄 scif_sas_smp_io_request.c(19.84 KB)
📄 scif_sas_smp_io_request.h(4.87 KB)
📄 scif_sas_smp_phy.c(11.61 KB)
📄 scif_sas_smp_phy.h(5.88 KB)
📄 scif_sas_smp_remote_device.c(92.85 KB)
📄 scif_sas_smp_remote_device.h(13.24 KB)
📄 scif_sas_stp_io_request.c(21.64 KB)
📄 scif_sas_stp_io_request.h(3.7 KB)
📄 scif_sas_stp_remote_device.c(7.46 KB)
📄 scif_sas_stp_remote_device.h(3.99 KB)
📄 scif_sas_stp_task_request.c(9.92 KB)
📄 scif_sas_stp_task_request.h(3.73 KB)
📄 scif_sas_task_request.c(16.16 KB)
📄 scif_sas_task_request.h(4.92 KB)
📄 scif_sas_task_request_state_handlers.c(13.5 KB)
📄 scif_sas_task_request_states.c(8.87 KB)
📄 scif_sas_timer.c(4.4 KB)
📄 scif_task_request.h(5.28 KB)
📄 scif_user_callback.h(37.98 KB)
📄 scu_bios_definitions.h(36.53 KB)
📄 scu_completion_codes.h(10.96 KB)
📄 scu_constants.h(6.55 KB)
📄 scu_event_codes.h(11.77 KB)
📄 scu_registers.h(83.65 KB)
📄 scu_remote_node_context.h(7.11 KB)
📄 scu_task_context.h(26.33 KB)
📄 scu_unsolicited_frame.h(4.1 KB)
📄 scu_viit_data.h(6.23 KB)

Editing: scic_sds_controller_registers.h

/*-
 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
 *
 * This file is provided under a dual BSD/GPLv2 license.  When using or
 * redistributing this file, you may do so under either license.
 *
 * GPL LICENSE SUMMARY
 *
 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 * The full GNU General Public License is included in this distribution
 * in the file called LICENSE.GPL.
 *
 * BSD LICENSE
 *
 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *   * Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *   * Redistributions in binary form must reproduce the above copyright
 *     notice, this list of conditions and the following disclaimer in
 *     the documentation and/or other materials provided with the
 *     distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * $FreeBSD$
 */
#ifndef _SCIC_SDS_CONTROLLER_REGISTERS_H_
#define _SCIC_SDS_CONTROLLER_REGISTERS_H_

/**
 * @file
 *
 * @brief This file contains macros used to perform the register reads/writes
 *        to the SCU hardware.
 */

#ifdef __cplusplus
extern "C" {
#endif // __cplusplus

#include <dev/isci/scil/scu_registers.h>
#include <dev/isci/scil/scic_sds_controller.h>

/**
 * @name SMU_REGISTER_ACCESS_MACROS
 */
/*@{*/
#define scic_sds_controller_smu_register_read(controller, reg) \
   smu_register_read( \
      (controller), \
      (controller)->smu_registers->reg \
   )

#define scic_sds_controller_smu_register_write(controller, reg, value) \
   smu_register_write( \
      (controller), \
      (controller)->smu_registers->reg, \
      (value) \
   )
/*@}*/

/**
 * @name AFE_REGISTER_ACCESS_MACROS
 */
/*@{*/
#define scu_afe_register_write(controller, reg, value) \
   scu_register_write( \
      (controller), \
      (controller)->scu_registers->afe.reg, \
      (value) \
   )

#define scu_afe_register_read(controller, reg) \
   scu_register_read( \
      (controller), \
      (controller)->scu_registers->afe.reg \
   )
/*@}*/

/**
 * @name SGPIO_PEG0_REGISTER_ACCESS_MACROS
 */
/*@{*/
#define scu_sgpio_peg0_register_read(controller, reg) \
   scu_register_read( \
      (controller), \
      (controller)->scu_registers->peg0.sgpio.reg \
   )

#define scu_sgpio_peg0_register_write(controller, reg, value) \
   scu_register_write( \
      (controller), \
      (controller)->scu_registers->peg0.sgpio.reg, \
      (value) \
   )
/*@}*/

/**
 * @name VIIT_REGISTER_ACCESS_MACROS
 */
/*@{*/
#define scu_controller_viit_register_write(controller, index, reg, value) \
   scu_register_write( \
      (controller), \
      (controller)->scu_registers->peg0.viit[index].reg, \
      value \
   )
/*@}*/

/**
 * @name SCRATCH_RAM_REGISTER_ACCESS_MACROS
 */
/*@{*/
// Scratch RAM access may be needed before the scu_registers pointer
//  has been initialized.  So instead, explicitly cast BAR1 to a
//  SCU_REGISTERS_T data structure.

// Scratch RAM is stored in the Zoning Permission Table for OROM use.
#define scu_controller_scratch_ram_register_write(controller, index, value) \
   scu_register_write( \
      (controller), \
      ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt0.table[index], \
      value \
   )

#define scu_controller_scratch_ram_register_read(controller, index) \
   scu_register_read( \
      (controller), \
      ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt0.table[index] \
   )

#define scu_controller_scratch_ram_register_write_ext(controller, index, value) \
   scu_register_write( \
      (controller), \
      ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt1.table[index], \
      value \
   )

#define scu_controller_scratch_ram_register_read_ext(controller, index) \
   scu_register_read( \
      (controller), \
      ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt1.table[index] \
   )
/*@}*/

//*****************************************************************************
//* SMU REGISTERS
//*****************************************************************************

/**
 * @name SMU_REGISTERS
 */
/*@{*/
#define SMU_PCP_WRITE(controller, value) \
    scic_sds_controller_smu_register_write( \
       controller, post_context_port, value \
    )

#define SMU_TCR_READ(controller, value) \
    scic_sds_controller_smu_register_read( \
       controller, task_context_range \
    )

#define SMU_TCR_WRITE(controller, value) \
    scic_sds_controller_smu_register_write( \
       controller, task_context_range, value \
    )

#define SMU_HTTBAR_WRITE(controller, address) \
{ \
   scic_sds_controller_smu_register_write( \
      controller, \
      host_task_table_lower, \
      sci_cb_physical_address_lower(address) \
   );\
   scic_sds_controller_smu_register_write( \
      controller, \
      host_task_table_upper, \
      sci_cb_physical_address_upper(address) \
   ); \
}

#define SMU_CQBAR_WRITE(controller, address) \
{ \
   scic_sds_controller_smu_register_write( \
      controller, \
      completion_queue_lower, \
      sci_cb_physical_address_lower(address) \
   ); \
   scic_sds_controller_smu_register_write( \
      controller, \
      completion_queue_upper, \
      sci_cb_physical_address_upper(address) \
   ); \
}

#define SMU_CQGR_WRITE(controller, value) \
    scic_sds_controller_smu_register_write( \
       controller, completion_queue_get, value \
    )

#define SMU_CQGR_READ(controller, value) \
    scic_sds_controller_smu_register_read( \
       controller, completion_queue_get \
    )

#define SMU_CQPR_WRITE(controller, value) \
    scic_sds_controller_smu_register_write( \
       controller, completion_queue_put, value \
    )

#define SMU_RNCBAR_WRITE(controller, address) \
{ \
   scic_sds_controller_smu_register_write( \
      controller, \
      remote_node_context_lower, \
      sci_cb_physical_address_lower(address) \
   ); \
   scic_sds_controller_smu_register_write( \
      controller, \
      remote_node_context_upper, \
      sci_cb_physical_address_upper(address) \
   ); \
}

#define SMU_AMR_READ(controller) \
   scic_sds_controller_smu_register_read( \
      controller, address_modifier \
   )

#define SMU_IMR_READ(controller) \
   scic_sds_controller_smu_register_read( \
      controller, interrupt_mask \
   )

#define SMU_IMR_WRITE(controller, mask) \
   scic_sds_controller_smu_register_write( \
      controller, interrupt_mask, mask \
   )

#define SMU_ISR_READ(controller) \
   scic_sds_controller_smu_register_read( \
      controller, interrupt_status \
   )

#define SMU_ISR_WRITE(controller, status) \
   scic_sds_controller_smu_register_write( \
      controller, interrupt_status, status \
   )

#define SMU_ICC_READ(controller) \
   scic_sds_controller_smu_register_read( \
      controller, interrupt_coalesce_control \
   )

#define SMU_ICC_WRITE(controller, value) \
   scic_sds_controller_smu_register_write( \
      controller, interrupt_coalesce_control, value \
   )

#define SMU_CQC_WRITE(controller, value) \
    scic_sds_controller_smu_register_write( \
       controller, completion_queue_control, value \
    )

#define SMU_SMUSRCR_WRITE(controller, value) \
   scic_sds_controller_smu_register_write( \
      controller, soft_reset_control, value \
   )

#define SMU_TCA_WRITE(controller, index, value) \
    scic_sds_controller_smu_register_write( \
       controller, task_context_assignment[index], value \
    )

#define SMU_TCA_READ(controller, index) \
    scic_sds_controller_smu_register_read( \
       controller, task_context_assignment[index] \
    )

#define SMU_DCC_READ(controller) \
   scic_sds_controller_smu_register_read( \
      controller, device_context_capacity \
   )

#define SMU_DFC_READ(controller) \
   scic_sds_controller_smu_register_read( \
      controller, device_function_capacity \
   )

#define SMU_SMUCSR_READ(controller) \
   scic_sds_controller_smu_register_read( \
      controller, control_status \
   )

#define SMU_CGUCR_READ(controller) \
   scic_sds_controller_smu_register_read( \
      controller, clock_gating_control \
   )

#define SMU_CGUCR_WRITE(controller, value) \
   scic_sds_controller_smu_register_write( \
      controller, clock_gating_control, value \
   )

#define SMU_CQPR_READ(controller) \
    scic_sds_controller_smu_register_read( \
       controller, completion_queue_put \
    )

/*@}*/

/**
 * @name SCU_REGISTER_ACCESS_MACROS
 */
/*@{*/
#define scic_sds_controller_scu_register_read(controller, reg) \
   scu_register_read( \
      (controller), \
      (controller)->scu_registers->reg \
   )

#define scic_sds_controller_scu_register_write(controller, reg, value) \
   scu_register_write( \
      (controller), \
      (controller)->scu_registers->reg, \
      (value) \
   )
/*@}*/

//****************************************************************************
//*  SCU SDMA REGISTERS
//****************************************************************************

/**
 * @name SCU_SDMA_REGISTER_ACCESS_MACROS
 */
/*@{*/
#define scu_sdma_register_read(controller, reg) \
   scu_register_read( \
      (controller), \
      (controller)->scu_registers->sdma.reg \
   )

#define scu_sdma_register_write(controller, reg, value) \
   scu_register_write( \
      (controller), \
      (controller)->scu_registers->sdma.reg, \
      (value) \
   )
/*@}*/

/**
 * @name SCU_SDMA_REGISTERS
 */
/*@{*/
#define SCU_PUFATHAR_WRITE(controller, address) \
{ \
   scu_sdma_register_write( \
      controller, \
      uf_address_table_lower, \
      sci_cb_physical_address_lower(address) \
   ); \
   scu_sdma_register_write( \
      controller, \
      uf_address_table_upper, \
      sci_cb_physical_address_upper(address) \
   ); \
}

#define SCU_UFHBAR_WRITE(controller, address) \
{ \
   scu_sdma_register_write( \
      controller, \
      uf_header_base_address_lower, \
      sci_cb_physical_address_lower(address) \
   ); \
   scu_sdma_register_write( \
      controller, \
      uf_header_base_address_upper, \
      sci_cb_physical_address_upper(address) \
   ); \
}

#define SCU_UFQC_READ(controller) \
    scu_sdma_register_read( \
       controller,  \
       unsolicited_frame_queue_control \
    )

#define SCU_UFQC_WRITE(controller, value) \
    scu_sdma_register_write( \
       controller, \
       unsolicited_frame_queue_control, \
       value \
    )

#define SCU_UFQPP_READ(controller) \
    scu_sdma_register_read( \
       controller, \
       unsolicited_frame_put_pointer \
    )

#define SCU_UFQPP_WRITE(controller, value) \
   scu_sdma_register_write( \
      controller, \
      unsolicited_frame_put_pointer, \
      value \
   )

#define SCU_UFQGP_WRITE(controller, value) \
   scu_sdma_register_write( \
      controller, \
      unsolicited_frame_get_pointer, \
      value \
   )

#define SCU_PDMACR_READ(controller) \
   scu_sdma_register_read( \
      controller, \
      pdma_configuration \
   )

#define SCU_PDMACR_WRITE(controller, value) \
   scu_sdma_register_write( \
      controller, \
      pdma_configuration, \
      value \
   )

#define SCU_CDMACR_READ(controller) \
   scu_sdma_register_read( \
     controller, \
     cdma_configuration \
   )

#define SCU_CDMACR_WRITE(controller, value) \
   scu_sdma_register_write( \
      controller, \
      cdma_configuration, \
      value \
   )
/*@}*/

//*****************************************************************************
//* SCU CRAM AND FBRAM Registers
//*****************************************************************************
/**
 * @name SCU_CRAM_REGISTER_ACCESS_MACROS
 */
/*@{*/
#define scu_cram_register_read(controller, reg) \
   scu_register_read( \
      (controller), \
      (controller)->scu_registers->cram.reg \
   )

#define scu_cram_register_write(controller, reg, value) \
   scu_register_write( \
      (controller), \
      (controller)->scu_registers->cram.reg, \
      (value) \
   )
/*@}*/

/**
 * @name SCU_FBRAM_REGISTER_ACCESS_MACROS
 */
/*@{*/
#define scu_fbram_register_read(controller, reg) \
   scu_register_read( \
      (controller), \
      (controller)->scu_registers->fbram.reg \
   )

#define scu_fbram_register_write(controller, reg, value) \
   scu_register_write( \
      (controller), \
      (controller)->scu_registers->fbram.reg, \
      (value) \
   )
/*@}*/

/**
 * @name SCU_CRAM_REGISTERS
 */
/*@{*/

// SRAM ECC CONTROL REGISTER BITS
#define SIGNLE_BIT_ERROR_CORRECTION_ENABLE 0x00000001
#define MULTI_BIT_ERROR_REPORTING_ENABLE   0x00000002
#define SINGLE_BIT_ERROR_REPORTING_ENABLE  0x00000004

//SRAM ECC control register (SECR0)
#define SCU_SECR0_WRITE(controller, value) \
    scu_cram_register_write( \
      controller, \
      sram_ecc_control_0, \
      value \
   )
/*@}*/

/**
 * @name SCU_FBRAM_REGISTERS
 */
/*@{*/

//SRAM ECC control register (SECR1)
#define SCU_SECR1_WRITE(controller, value) \
    scu_fbram_register_write( \
      controller, \
      sram_ecc_control_1, \
      value \
   )
/*@}*/

//*****************************************************************************
//* SCU Port Task Scheduler Group Registers
//*****************************************************************************

/**
 * @name SCU_PTSG_REGISTER_ACCESS_MACROS
 */
/*@{*/
#define scu_ptsg_register_read(controller, reg) \
   scu_register_read( \
      (controller), \
      (controller)->scu_registers->peg0.ptsg.reg \
   )

#define scu_ptsg_register_write(controller, reg, value) \
   scu_register_write( \
      (controller), \
      (controller)->scu_registers->peg0.ptsg.reg, \
      (value) \
   )
/*@}*/

/**
 * @name SCU_PTSG_REGISTERS
 */
/*@{*/
#define SCU_PTSGCR_READ(controller) \
    scu_ptsg_register_read( \
       (controller), \
       control \
    )

#define SCU_PTSGCR_WRITE(controller, value) \
    scu_ptsg_register_write( \
       (controller), \
       control, \
       value \
    )

#define SCU_PTSGRTC_READ(controller) \
    scu_ptsg_register_read( \
       controller, \
       real_time_clock \
    )
/*@}*/

#ifdef __cplusplus
}
#endif // __cplusplus

#endif // _SCIC_SDS_CONTROLLER_REGISTERS_H_

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