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📄 ef10_ev.c(38.47 KB)
📄 ef10_filter.c(48.25 KB)
📄 ef10_image.c(22.76 KB)
📄 ef10_impl.h(28.32 KB)
📄 ef10_intr.c(4.71 KB)
📄 ef10_mac.c(31.92 KB)
📄 ef10_mcdi.c(9.59 KB)
📄 ef10_nic.c(62.96 KB)
📄 ef10_nvram.c(54.36 KB)
📄 ef10_phy.c(20.26 KB)
📄 ef10_rx.c(30.8 KB)
📄 ef10_signed_image_layout.h(3.9 KB)
📄 ef10_tlv_layout.h(33.34 KB)
📄 ef10_tx.c(19.03 KB)
📄 ef10_vpd.c(11.03 KB)
📄 efsys.h(31.95 KB)
📄 efx.h(82.48 KB)
📄 efx_annote.h(4.06 KB)
📄 efx_bootcfg.c(25.55 KB)
📄 efx_check.h(11.67 KB)
📄 efx_crc32.c(5.45 KB)
📄 efx_ev.c(34.49 KB)
📄 efx_filter.c(39.47 KB)
📄 efx_hash.c(8.08 KB)
📄 efx_impl.h(38.52 KB)
📄 efx_intr.c(14.56 KB)
📄 efx_lic.c(37.43 KB)
📄 efx_mac.c(22.27 KB)
📄 efx_mcdi.c(58.17 KB)
📄 efx_mcdi.h(13.28 KB)
📄 efx_mon.c(23.85 KB)
📄 efx_nic.c(28.89 KB)
📄 efx_nvram.c(24.9 KB)
📄 efx_phy.c(13.44 KB)
📄 efx_phy_ids.h(2.04 KB)
📄 efx_port.c(5.99 KB)
📄 efx_regs.h(118.32 KB)
📄 efx_regs_ef10.h(21.93 KB)
📄 efx_regs_mcdi.h(769.41 KB)
📄 efx_regs_mcdi_aoe.h(125.41 KB)
📄 efx_regs_mcdi_strs.h(8.54 KB)
📄 efx_regs_pci.h(55.57 KB)
📄 efx_rx.c(39.55 KB)
📄 efx_sram.c(8.76 KB)
📄 efx_tunnel.c(11.69 KB)
📄 efx_tx.c(27.1 KB)
📄 efx_types.h(57.59 KB)
📄 efx_vpd.c(20.8 KB)
📄 hunt_impl.h(2.36 KB)
📄 hunt_nic.c(7.76 KB)
📄 mcdi_mon.c(16.08 KB)
📄 mcdi_mon.h(2.47 KB)
📄 medford2_impl.h(2.1 KB)
📄 medford2_nic.c(5.53 KB)
📄 medford_impl.h(2.04 KB)
📄 medford_nic.c(5.39 KB)
📄 siena_flash.h(9.02 KB)
📄 siena_impl.h(10.2 KB)
📄 siena_mac.c(15.58 KB)
📄 siena_mcdi.c(6.87 KB)
📄 siena_nic.c(20.68 KB)
📄 siena_nvram.c(17.89 KB)
📄 siena_phy.c(22.34 KB)
📄 siena_sram.c(5.46 KB)
📄 siena_vpd.c(14.54 KB)

Editing: siena_sram.c

/*-
 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
 *
 * Copyright (c) 2009-2016 Solarflare Communications Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following disclaimer in the documentation
 *    and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * The views and conclusions contained in the software and documentation are
 * those of the authors and should not be interpreted as representing official
 * policies, either expressed or implied, of the FreeBSD Project.
 */

#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");

#include "efx.h"
#include "efx_impl.h"

#if EFSYS_OPT_SIENA

void
siena_sram_init(
	__in		efx_nic_t *enp)
{
	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
	efx_oword_t oword;
	uint32_t rx_base, tx_base;

EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
	EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA);

rx_base = encp->enc_buftbl_limit;
	tx_base = rx_base + (encp->enc_rxq_limit *
	    EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE));

/* Initialize the transmit descriptor cache */
	EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_TX_DC_BASE_ADR, tx_base);
	EFX_BAR_WRITEO(enp, FR_AZ_SRM_TX_DC_CFG_REG, &oword);

EFX_POPULATE_OWORD_1(oword, FRF_AZ_TX_DC_SIZE, EFX_TXQ_DC_SIZE);
	EFX_BAR_WRITEO(enp, FR_AZ_TX_DC_CFG_REG, &oword);

/* Initialize the receive descriptor cache */
	EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_RX_DC_BASE_ADR, rx_base);
	EFX_BAR_WRITEO(enp, FR_AZ_SRM_RX_DC_CFG_REG, &oword);

EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_SIZE, EFX_RXQ_DC_SIZE);
	EFX_BAR_WRITEO(enp, FR_AZ_RX_DC_CFG_REG, &oword);

/* Set receive descriptor pre-fetch low water mark */
	EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_PF_LWM, 56);
	EFX_BAR_WRITEO(enp, FR_AZ_RX_DC_PF_WM_REG, &oword);

/* Set the event queue to use for SRAM updates */
	EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_UPD_EVQ_ID, 0);
	EFX_BAR_WRITEO(enp, FR_AZ_SRM_UPD_EVQ_REG, &oword);
}

#if EFSYS_OPT_DIAG

__checkReturn	efx_rc_t
siena_sram_test(
	__in		efx_nic_t *enp,
	__in		efx_sram_pattern_fn_t func)
{
	efx_oword_t oword;
	efx_qword_t qword;
	efx_qword_t verify;
	size_t rows;
	unsigned int wptr;
	unsigned int rptr;
	efx_rc_t rc;

EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA);

/* Reconfigure into HALF buffer table mode */
	EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 0);
	EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);

/*
	 * Move the descriptor caches up to the top of SRAM, and test
	 * all of SRAM below them. We only miss out one row here.
	 */
	rows = SIENA_SRAM_ROWS - 1;
	EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_RX_DC_BASE_ADR, rows);
	EFX_BAR_WRITEO(enp, FR_AZ_SRM_RX_DC_CFG_REG, &oword);

EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_TX_DC_BASE_ADR, rows + 1);
	EFX_BAR_WRITEO(enp, FR_AZ_SRM_TX_DC_CFG_REG, &oword);

/*
	 * Write the pattern through BUF_HALF_TBL. Write
	 * in 64 entry batches, waiting 1us in between each batch
	 * to guarantee not to overflow the SRAM fifo
	 */
	for (wptr = 0, rptr = 0; wptr < rows; ++wptr) {
		func(wptr, B_FALSE, &qword);
		EFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_HALF_TBL, wptr, &qword);

if ((wptr - rptr) < 64 && wptr < rows - 1)
			continue;

EFSYS_SPIN(1);

for (; rptr <= wptr; ++rptr) {
			func(rptr, B_FALSE, &qword);
			EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_HALF_TBL, rptr,
			    &verify);

if (!EFX_QWORD_IS_EQUAL(verify, qword)) {
				rc = EFAULT;
				goto fail1;
			}
		}
	}

/* And do the same negated */
	for (wptr = 0, rptr = 0; wptr < rows; ++wptr) {
		func(wptr, B_TRUE, &qword);
		EFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_HALF_TBL, wptr, &qword);

if ((wptr - rptr) < 64 && wptr < rows - 1)
			continue;

EFSYS_SPIN(1);

for (; rptr <= wptr; ++rptr) {
			func(rptr, B_TRUE, &qword);
			EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_HALF_TBL, rptr,
			    &verify);

if (!EFX_QWORD_IS_EQUAL(verify, qword)) {
				rc = EFAULT;
				goto fail2;
			}
		}
	}

/* Restore back to FULL buffer table mode */
	EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 1);
	EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);

/*
	 * We don't need to reconfigure SRAM again because the API
	 * requires efx_nic_fini() to be called after an sram test.
	 */
	return (0);

fail2:
	EFSYS_PROBE(fail2);
fail1:
	EFSYS_PROBE1(fail1, efx_rc_t, rc);

/* Restore back to FULL buffer table mode */
	EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 1);
	EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);

return (rc);
}

#endif	/* EFSYS_OPT_DIAG */

#endif	/* EFSYS_OPT_SIENA */

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Editing: siena_sram.c

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