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files.socfpga
(650 B)
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socfpga_a10_manager.c
(10.31 KB)
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socfpga_common.c
(1.81 KB)
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socfpga_common.h
(1.94 KB)
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socfpga_l3regs.h
(2.81 KB)
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socfpga_machdep.c
(4.55 KB)
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socfpga_manager.c
(10.76 KB)
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socfpga_mp.c
(6.11 KB)
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socfpga_mp.h
(1.51 KB)
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socfpga_rstmgr.c
(5.97 KB)
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socfpga_rstmgr.h
(2.32 KB)
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std.socfpga
(131 B)
Editing: socfpga_common.h
/*- * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> * All rights reserved. * * This software was developed by SRI International and the University of * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) * ("CTSRD"), as part of the DARPA CRASH research programme. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #define READ4(_sc, _reg) bus_read_4((_sc)->res[0], _reg) #define READ2(_sc, _reg) bus_read_2((_sc)->res[0], _reg) #define READ1(_sc, _reg) bus_read_1((_sc)->res[0], _reg) #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val) #define WRITE2(_sc, _reg, _val) bus_write_2((_sc)->res[0], _reg, _val) #define WRITE1(_sc, _reg, _val) bus_write_1((_sc)->res[0], _reg, _val)
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