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Makefile.in
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THIRDPARTYLICENSE.cityhash
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THIRDPARTYLICENSE.cityhash.descrip
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abd.c
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aggsum.c
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arc.c
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blkptr.c
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bplist.c
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bpobj.c
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bptree.c
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bqueue.c
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btree.c
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dataset_kstats.c
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dbuf.c
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dbuf_stats.c
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ddt.c
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ddt_zap.c
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dmu.c
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dmu_diff.c
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dmu_object.c
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dmu_objset.c
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dmu_recv.c
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dmu_redact.c
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dmu_send.c
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dmu_traverse.c
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dmu_tx.c
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dmu_zfetch.c
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dnode.c
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dnode_sync.c
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dsl_bookmark.c
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dsl_crypt.c
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dsl_dataset.c
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dsl_deadlist.c
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dsl_deleg.c
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dsl_destroy.c
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dsl_dir.c
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dsl_pool.c
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dsl_prop.c
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dsl_scan.c
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dsl_synctask.c
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dsl_userhold.c
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edonr_zfs.c
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fm.c
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gzip.c
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hkdf.c
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lz4.c
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lzjb.c
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metaslab.c
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mmp.c
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multilist.c
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objlist.c
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pathname.c
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range_tree.c
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refcount.c
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rrwlock.c
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sa.c
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sha256.c
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skein_zfs.c
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spa.c
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spa_boot.c
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spa_checkpoint.c
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spa_config.c
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spa_errlog.c
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spa_history.c
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spa_log_spacemap.c
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spa_misc.c
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spa_stats.c
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space_map.c
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space_reftree.c
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txg.c
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uberblock.c
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unique.c
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vdev.c
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vdev_cache.c
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vdev_draid.c
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vdev_draid_rand.c
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vdev_indirect.c
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vdev_indirect_births.c
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vdev_indirect_mapping.c
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vdev_initialize.c
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vdev_label.c
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vdev_mirror.c
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vdev_missing.c
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vdev_queue.c
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vdev_raidz.c
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vdev_raidz_math.c
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vdev_raidz_math_aarch64_neon.c
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vdev_raidz_math_aarch64_neon_common.h
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vdev_raidz_math_aarch64_neonx2.c
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vdev_raidz_math_avx2.c
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vdev_raidz_math_avx512bw.c
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vdev_raidz_math_avx512f.c
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vdev_raidz_math_impl.h
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vdev_raidz_math_powerpc_altivec.c
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vdev_raidz_math_powerpc_altivec_common.h
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vdev_raidz_math_scalar.c
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vdev_raidz_math_sse2.c
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vdev_raidz_math_ssse3.c
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vdev_rebuild.c
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vdev_removal.c
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vdev_root.c
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vdev_trim.c
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zap.c
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zap_leaf.c
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zap_micro.c
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zcp.c
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zcp_get.c
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zcp_global.c
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zcp_iter.c
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zcp_set.c
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zcp_synctask.c
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zfeature.c
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zfs_byteswap.c
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zfs_fm.c
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zfs_fuid.c
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zfs_ioctl.c
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zfs_log.c
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zfs_onexit.c
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zfs_quota.c
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zfs_ratelimit.c
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zfs_replay.c
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zfs_rlock.c
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zfs_sa.c
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zfs_vnops.c
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zil.c
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zio.c
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zio_checksum.c
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zio_compress.c
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zio_inject.c
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zle.c
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zrlock.c
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zthr.c
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zvol.c
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Editing: vdev_raidz_math_ssse3.c
/* * CDDL HEADER START * * The contents of this file are subject to the terms of the * Common Development and Distribution License (the "License"). * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. * See the License for the specific language governing permissions * and limitations under the License. * * When distributing Covered Code, include this CDDL HEADER in each * file and include the License file at usr/src/OPENSOLARIS.LICENSE. * If applicable, add the following below this CDDL HEADER, with the * fields enclosed by brackets "[]" replaced with your own identifying * information: Portions Copyright [yyyy] [name of copyright owner] * * CDDL HEADER END */ /* * Copyright (C) 2016 Gvozden NeΕ‘koviΔ. All rights reserved. */ #include <sys/isa_defs.h> #if defined(__x86_64) && defined(HAVE_SSSE3) #include <sys/types.h> #include <sys/simd.h> #ifdef __linux__ #define __asm __asm__ __volatile__ #endif #define _REG_CNT(_0, _1, _2, _3, _4, _5, _6, _7, N, ...) N #define REG_CNT(r...) _REG_CNT(r, 8, 7, 6, 5, 4, 3, 2, 1) #define VR0_(REG, ...) "xmm"#REG #define VR1_(_1, REG, ...) "xmm"#REG #define VR2_(_1, _2, REG, ...) "xmm"#REG #define VR3_(_1, _2, _3, REG, ...) "xmm"#REG #define VR4_(_1, _2, _3, _4, REG, ...) "xmm"#REG #define VR5_(_1, _2, _3, _4, _5, REG, ...) "xmm"#REG #define VR6_(_1, _2, _3, _4, _5, _6, REG, ...) "xmm"#REG #define VR7_(_1, _2, _3, _4, _5, _6, _7, REG, ...) "xmm"#REG #define VR0(r...) VR0_(r) #define VR1(r...) VR1_(r) #define VR2(r...) VR2_(r, 1) #define VR3(r...) VR3_(r, 1, 2) #define VR4(r...) VR4_(r, 1, 2) #define VR5(r...) VR5_(r, 1, 2, 3) #define VR6(r...) VR6_(r, 1, 2, 3, 4) #define VR7(r...) VR7_(r, 1, 2, 3, 4, 5) #define R_01(REG1, REG2, ...) REG1, REG2 #define _R_23(_0, _1, REG2, REG3, ...) REG2, REG3 #define R_23(REG...) _R_23(REG, 1, 2, 3) #define ZFS_ASM_BUG() ASSERT(0) const uint8_t gf_clmul_mod_lt[4*256][16]; #define ELEM_SIZE 16 typedef struct v { uint8_t b[ELEM_SIZE] __attribute__((aligned(ELEM_SIZE))); } v_t; #define XOR_ACC(src, r...) \ { \ switch (REG_CNT(r)) { \ case 4: \ __asm( \ "pxor 0x00(%[SRC]), %%" VR0(r) "\n" \ "pxor 0x10(%[SRC]), %%" VR1(r) "\n" \ "pxor 0x20(%[SRC]), %%" VR2(r) "\n" \ "pxor 0x30(%[SRC]), %%" VR3(r) "\n" \ : : [SRC] "r" (src)); \ break; \ case 2: \ __asm( \ "pxor 0x00(%[SRC]), %%" VR0(r) "\n" \ "pxor 0x10(%[SRC]), %%" VR1(r) "\n" \ : : [SRC] "r" (src)); \ break; \ default: \ ZFS_ASM_BUG(); \ } \ } #define XOR(r...) \ { \ switch (REG_CNT(r)) { \ case 8: \ __asm( \ "pxor %" VR0(r) ", %" VR4(r) "\n" \ "pxor %" VR1(r) ", %" VR5(r) "\n" \ "pxor %" VR2(r) ", %" VR6(r) "\n" \ "pxor %" VR3(r) ", %" VR7(r)); \ break; \ case 4: \ __asm( \ "pxor %" VR0(r) ", %" VR2(r) "\n" \ "pxor %" VR1(r) ", %" VR3(r)); \ break; \ default: \ ZFS_ASM_BUG(); \ } \ } #define ZERO(r...) XOR(r, r) #define COPY(r...) \ { \ switch (REG_CNT(r)) { \ case 8: \ __asm( \ "movdqa %" VR0(r) ", %" VR4(r) "\n" \ "movdqa %" VR1(r) ", %" VR5(r) "\n" \ "movdqa %" VR2(r) ", %" VR6(r) "\n" \ "movdqa %" VR3(r) ", %" VR7(r)); \ break; \ case 4: \ __asm( \ "movdqa %" VR0(r) ", %" VR2(r) "\n" \ "movdqa %" VR1(r) ", %" VR3(r)); \ break; \ default: \ ZFS_ASM_BUG(); \ } \ } #define LOAD(src, r...) \ { \ switch (REG_CNT(r)) { \ case 4: \ __asm( \ "movdqa 0x00(%[SRC]), %%" VR0(r) "\n" \ "movdqa 0x10(%[SRC]), %%" VR1(r) "\n" \ "movdqa 0x20(%[SRC]), %%" VR2(r) "\n" \ "movdqa 0x30(%[SRC]), %%" VR3(r) "\n" \ : : [SRC] "r" (src)); \ break; \ case 2: \ __asm( \ "movdqa 0x00(%[SRC]), %%" VR0(r) "\n" \ "movdqa 0x10(%[SRC]), %%" VR1(r) "\n" \ : : [SRC] "r" (src)); \ break; \ default: \ ZFS_ASM_BUG(); \ } \ } #define STORE(dst, r...) \ { \ switch (REG_CNT(r)) { \ case 4: \ __asm( \ "movdqa %%" VR0(r)", 0x00(%[DST])\n" \ "movdqa %%" VR1(r)", 0x10(%[DST])\n" \ "movdqa %%" VR2(r)", 0x20(%[DST])\n" \ "movdqa %%" VR3(r)", 0x30(%[DST])\n" \ : : [DST] "r" (dst)); \ break; \ case 2: \ __asm( \ "movdqa %%" VR0(r)", 0x00(%[DST])\n" \ "movdqa %%" VR1(r)", 0x10(%[DST])\n" \ : : [DST] "r" (dst)); \ break; \ default: \ ZFS_ASM_BUG(); \ } \ } #define MUL2_SETUP() \ { \ __asm( \ "movd %[mask], %%xmm15\n" \ "pshufd $0x0, %%xmm15, %%xmm15\n" \ : : [mask] "r" (0x1d1d1d1d)); \ } #define _MUL2_x2(r...) \ { \ switch (REG_CNT(r)) { \ case 2: \ __asm( \ "pxor %xmm14, %xmm14\n" \ "pxor %xmm13, %xmm13\n" \ "pcmpgtb %" VR0(r)", %xmm14\n" \ "pcmpgtb %" VR1(r)", %xmm13\n" \ "pand %xmm15, %xmm14\n" \ "pand %xmm15, %xmm13\n" \ "paddb %" VR0(r)", %" VR0(r) "\n" \ "paddb %" VR1(r)", %" VR1(r) "\n" \ "pxor %xmm14, %" VR0(r) "\n" \ "pxor %xmm13, %" VR1(r)); \ break; \ default: \ ZFS_ASM_BUG(); \ } \ } #define MUL2(r...) \ { \ switch (REG_CNT(r)) { \ case 4: \ _MUL2_x2(R_01(r)); \ _MUL2_x2(R_23(r)); \ break; \ case 2: \ _MUL2_x2(r); \ break; \ default: \ ZFS_ASM_BUG(); \ } \ } #define MUL4(r...) \ { \ MUL2(r); \ MUL2(r); \ } #define _0f "xmm15" #define _a_save "xmm14" #define _b_save "xmm13" #define _lt_mod_a "xmm12" #define _lt_clmul_a "xmm11" #define _lt_mod_b "xmm10" #define _lt_clmul_b "xmm15" #define _MULx2(c, r...) \ { \ switch (REG_CNT(r)) { \ case 2: \ __asm( \ /* lts for upper part */ \ "movd %[mask], %%" _0f "\n" \ "pshufd $0x0, %%" _0f ", %%" _0f "\n" \ "movdqa 0x00(%[lt]), %%" _lt_mod_a "\n" \ "movdqa 0x10(%[lt]), %%" _lt_clmul_a "\n" \ /* upper part */ \ "movdqa %%" VR0(r) ", %%" _a_save "\n" \ "movdqa %%" VR1(r) ", %%" _b_save "\n" \ "psraw $0x4, %%" VR0(r) "\n" \ "psraw $0x4, %%" VR1(r) "\n" \ "pand %%" _0f ", %%" _a_save "\n" \ "pand %%" _0f ", %%" _b_save "\n" \ "pand %%" _0f ", %%" VR0(r) "\n" \ "pand %%" _0f ", %%" VR1(r) "\n" \ \ "movdqa %%" _lt_mod_a ", %%" _lt_mod_b "\n" \ "movdqa %%" _lt_clmul_a ", %%" _lt_clmul_b "\n" \ \ "pshufb %%" VR0(r) ",%%" _lt_mod_a "\n" \ "pshufb %%" VR1(r) ",%%" _lt_mod_b "\n" \ "pshufb %%" VR0(r) ",%%" _lt_clmul_a "\n" \ "pshufb %%" VR1(r) ",%%" _lt_clmul_b "\n" \ \ "pxor %%" _lt_mod_a ",%%" _lt_clmul_a "\n" \ "pxor %%" _lt_mod_b ",%%" _lt_clmul_b "\n" \ "movdqa %%" _lt_clmul_a ",%%" VR0(r) "\n" \ "movdqa %%" _lt_clmul_b ",%%" VR1(r) "\n" \ /* lts for lower part */ \ "movdqa 0x20(%[lt]), %%" _lt_mod_a "\n" \ "movdqa 0x30(%[lt]), %%" _lt_clmul_a "\n" \ "movdqa %%" _lt_mod_a ", %%" _lt_mod_b "\n" \ "movdqa %%" _lt_clmul_a ", %%" _lt_clmul_b "\n" \ /* lower part */ \ "pshufb %%" _a_save ",%%" _lt_mod_a "\n" \ "pshufb %%" _b_save ",%%" _lt_mod_b "\n" \ "pshufb %%" _a_save ",%%" _lt_clmul_a "\n" \ "pshufb %%" _b_save ",%%" _lt_clmul_b "\n" \ \ "pxor %%" _lt_mod_a ",%%" VR0(r) "\n" \ "pxor %%" _lt_mod_b ",%%" VR1(r) "\n" \ "pxor %%" _lt_clmul_a ",%%" VR0(r) "\n" \ "pxor %%" _lt_clmul_b ",%%" VR1(r) "\n" \ : : [mask] "r" (0x0f0f0f0f), \ [lt] "r" (gf_clmul_mod_lt[4*(c)])); \ break; \ default: \ ZFS_ASM_BUG(); \ } \ } #define MUL(c, r...) \ { \ switch (REG_CNT(r)) { \ case 4: \ _MULx2(c, R_23(r)); \ _MULx2(c, R_01(r)); \ break; \ case 2: \ _MULx2(c, R_01(r)); \ break; \ default: \ ZFS_ASM_BUG(); \ } \ } #define raidz_math_begin() kfpu_begin() #define raidz_math_end() kfpu_end() #define SYN_STRIDE 4 #define ZERO_STRIDE 4 #define ZERO_DEFINE() {} #define ZERO_D 0, 1, 2, 3 #define COPY_STRIDE 4 #define COPY_DEFINE() {} #define COPY_D 0, 1, 2, 3 #define ADD_STRIDE 4 #define ADD_DEFINE() {} #define ADD_D 0, 1, 2, 3 #define MUL_STRIDE 4 #define MUL_DEFINE() {} #define MUL_D 0, 1, 2, 3 #define GEN_P_STRIDE 4 #define GEN_P_DEFINE() {} #define GEN_P_P 0, 1, 2, 3 #define GEN_PQ_STRIDE 4 #define GEN_PQ_DEFINE() {} #define GEN_PQ_D 0, 1, 2, 3 #define GEN_PQ_C 4, 5, 6, 7 #define GEN_PQR_STRIDE 4 #define GEN_PQR_DEFINE() {} #define GEN_PQR_D 0, 1, 2, 3 #define GEN_PQR_C 4, 5, 6, 7 #define SYN_Q_DEFINE() {} #define SYN_Q_D 0, 1, 2, 3 #define SYN_Q_X 4, 5, 6, 7 #define SYN_R_DEFINE() {} #define SYN_R_D 0, 1, 2, 3 #define SYN_R_X 4, 5, 6, 7 #define SYN_PQ_DEFINE() {} #define SYN_PQ_D 0, 1, 2, 3 #define SYN_PQ_X 4, 5, 6, 7 #define REC_PQ_STRIDE 2 #define REC_PQ_DEFINE() {} #define REC_PQ_X 0, 1 #define REC_PQ_Y 2, 3 #define REC_PQ_T 4, 5 #define SYN_PR_DEFINE() {} #define SYN_PR_D 0, 1, 2, 3 #define SYN_PR_X 4, 5, 6, 7 #define REC_PR_STRIDE 2 #define REC_PR_DEFINE() {} #define REC_PR_X 0, 1 #define REC_PR_Y 2, 3 #define REC_PR_T 4, 5 #define SYN_QR_DEFINE() {} #define SYN_QR_D 0, 1, 2, 3 #define SYN_QR_X 4, 5, 6, 7 #define REC_QR_STRIDE 2 #define REC_QR_DEFINE() {} #define REC_QR_X 0, 1 #define REC_QR_Y 2, 3 #define REC_QR_T 4, 5 #define SYN_PQR_DEFINE() {} #define SYN_PQR_D 0, 1, 2, 3 #define SYN_PQR_X 4, 5, 6, 7 #define REC_PQR_STRIDE 2 #define REC_PQR_DEFINE() {} #define REC_PQR_X 0, 1 #define REC_PQR_Y 2, 3 #define REC_PQR_Z 4, 5 #define REC_PQR_XS 6, 7 #define REC_PQR_YS 8, 9 #include <sys/vdev_raidz_impl.h> #include "vdev_raidz_math_impl.h" DEFINE_GEN_METHODS(ssse3); DEFINE_REC_METHODS(ssse3); static boolean_t raidz_will_ssse3_work(void) { return (kfpu_allowed() && zfs_sse_available() && zfs_sse2_available() && zfs_ssse3_available()); } const raidz_impl_ops_t vdev_raidz_ssse3_impl = { .init = NULL, .fini = NULL, .gen = RAIDZ_GEN_METHODS(ssse3), .rec = RAIDZ_REC_METHODS(ssse3), .is_supported = &raidz_will_ssse3_work, .name = "ssse3" }; #endif /* defined(__x86_64) && defined(HAVE_SSSE3) */ #if defined(__x86_64) #if defined(HAVE_SSSE3) || defined(HAVE_AVX2) || defined(HAVE_AVX512BW) /* BEGIN CSTYLED */ const uint8_t __attribute__((aligned(256))) gf_clmul_mod_lt[4*256][16] = { { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 0x80, 0x90, 0xa0, 0xb0, 0xc0, 0xd0, 0xe0, 0xf0 }, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f }, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d }, { 0x00, 0x20, 0x40, 0x60, 0x80, 0xa0, 0xc0, 0xe0, 0x00, 0x20, 0x40, 0x60, 0x80, 0xa0, 0xc0, 0xe0 }, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x00, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e }, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d }, { 0x00, 0x30, 0x60, 0x50, 0xc0, 0xf0, 0xa0, 0x90, 0x80, 0xb0, 0xe0, 0xd0, 0x40, 0x70, 0x20, 0x10 }, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 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0x00, 0x60, 0xc0, 0xa0, 0x80, 0xe0, 0x40, 0x20, 0x00, 0x60, 0xc0, 0xa0, 0x80, 0xe0, 0x40, 0x20 }, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x00, 0x06, 0x0c, 0x0a, 0x18, 0x1e, 0x14, 0x12, 0x30, 0x36, 0x3c, 0x3a, 0x28, 0x2e, 0x24, 0x22 }, { 0x00, 0x00, 0x00, 0x00, 0x1d, 0x1d, 0x1d, 0x1d, 0x27, 0x27, 0x27, 0x27, 0x3a, 0x3a, 0x3a, 0x3a }, { 0x00, 0x70, 0xe0, 0x90, 0xc0, 0xb0, 0x20, 0x50, 0x80, 0xf0, 0x60, 0x10, 0x40, 0x30, 0xa0, 0xd0 }, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15, 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d }, { 0x00, 0x00, 0x1d, 0x1d, 0x3a, 0x3a, 0x27, 0x27, 0x74, 0x74, 0x69, 0x69, 0x4e, 0x4e, 0x53, 0x53 }, { 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80 }, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, { 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0x00, 0xfd, 0xfa, 0x07, 0xf4, 0x09, 0x0e, 0xf3, 0xe8, 0x15, 0x12, 0xef, 0x1c, 0xe1, 0xe6, 0x1b }, { 0x00, 0xbb, 0x76, 0xcd, 0xf1, 0x4a, 0x87, 0x3c, 0xe2, 0x59, 0x94, 0x2f, 0x13, 0xa8, 0x65, 0xde }, { 0x00, 0xe0, 0xc0, 0x20, 0x80, 0x60, 0x40, 0xa0, 0x00, 0xe0, 0xc0, 0x20, 0x80, 0x60, 0x40, 0xa0 }, { 0x00, 0x00, 0x1d, 0x1d, 0x27, 0x27, 0x3a, 0x3a, 0x53, 0x53, 0x4e, 0x4e, 0x74, 0x74, 0x69, 0x69 }, { 0x00, 0xfe, 0xfc, 0x02, 0xf8, 0x06, 0x04, 0xfa, 0xf0, 0x0e, 0x0c, 0xf2, 0x08, 0xf6, 0xf4, 0x0a }, { 0x00, 0xbb, 0x76, 0xcd, 0xf1, 0x4a, 0x87, 0x3c, 0xe2, 0x59, 0x94, 0x2f, 0x13, 0xa8, 0x65, 0xde }, { 0x00, 0xf0, 0xe0, 0x10, 0xc0, 0x30, 0x20, 0xd0, 0x80, 0x70, 0x60, 0x90, 0x40, 0xb0, 0xa0, 0x50 }, { 0x00, 0x00, 0x1d, 0x1d, 0x27, 0x27, 0x3a, 0x3a, 0x53, 0x53, 0x4e, 0x4e, 0x74, 0x74, 0x69, 0x69 }, { 0x00, 0xff, 0xfe, 0x01, 0xfc, 0x03, 0x02, 0xfd, 0xf8, 0x07, 0x06, 0xf9, 0x04, 0xfb, 0xfa, 0x05 } }; /* END CSTYLED */ #endif /* defined(HAVE_SSSE3) || defined(HAVE_AVX2) || defined(HAVE_AVX512BW) */ #endif /* defined(__x86_64) */
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