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altera-fpga2sdram-bridge.txt
(353 B)
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altera-freeze-bridge.txt
(697 B)
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altera-hps2fpga-bridge.txt
(1.02 KB)
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altera-passive-serial.txt
(988 B)
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altera-pr-ip.txt
(276 B)
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altera-socfpga-a10-fpga-mgr.txt
(629 B)
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altera-socfpga-fpga-mgr.txt
(533 B)
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fpga-bridge.txt
(367 B)
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fpga-region.txt
(17.25 KB)
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intel-stratix10-soc-fpga-mgr.txt
(372 B)
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lattice-ice40-fpga-mgr.txt
(729 B)
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lattice-machxo2-spi.txt
(656 B)
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xilinx-pr-decoupler.txt
(1.12 KB)
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xilinx-slave-serial.txt
(1.62 KB)
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xilinx-zynq-fpga-mgr.txt
(560 B)
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xlnx,zynqmp-pcap-fpga.txt
(641 B)
Editing: xilinx-pr-decoupler.txt
Xilinx LogiCORE Partial Reconfig Decoupler Softcore The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more decouplers / fpga bridges. The controller can decouple/disable the bridges which prevents signal changes from passing through the bridge. The controller can also couple / enable the bridges which allows traffic to pass through the bridge normally. The Driver supports only MMIO handling. A PR region can have multiple PR Decouplers which can be handled independently or chained via decouple/ decouple_status signals. Required properties: - compatible : Should contain "xlnx,pr-decoupler-1.00" followed by "xlnx,pr-decoupler" - regs : base address and size for decoupler module - clocks : input clock to IP - clock-names : should contain "aclk" See Documentation/devicetree/bindings/fpga/fpga-region.txt and Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings. Example: fpga-bridge@100000450 { compatible = "xlnx,pr-decoupler-1.00", "xlnx-pr-decoupler"; regs = <0x10000045 0x10>; clocks = <&clkc 15>; clock-names = "aclk"; bridge-enable = <0>; };
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