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altera-fpga2sdram-bridge.txt
(353 B)
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altera-freeze-bridge.txt
(697 B)
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altera-hps2fpga-bridge.txt
(1.02 KB)
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altera-passive-serial.txt
(988 B)
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altera-pr-ip.txt
(276 B)
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altera-socfpga-a10-fpga-mgr.txt
(629 B)
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altera-socfpga-fpga-mgr.txt
(533 B)
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fpga-bridge.txt
(367 B)
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fpga-region.txt
(17.25 KB)
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intel-stratix10-soc-fpga-mgr.txt
(372 B)
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lattice-ice40-fpga-mgr.txt
(729 B)
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lattice-machxo2-spi.txt
(656 B)
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xilinx-pr-decoupler.txt
(1.12 KB)
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xilinx-slave-serial.txt
(1.62 KB)
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xilinx-zynq-fpga-mgr.txt
(560 B)
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xlnx,zynqmp-pcap-fpga.txt
(641 B)
Editing: xilinx-zynq-fpga-mgr.txt
Xilinx Zynq FPGA Manager Required properties: - compatible: should contain "xlnx,zynq-devcfg-1.0" - reg: base address and size for memory mapped io - interrupts: interrupt for the FPGA manager device - clocks: phandle for clocks required operation - clock-names: name for the clock, should be "ref_clk" - syscon: phandle for access to SLCR registers Example: devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; reg = <0xf8007000 0x100>; interrupts = <0 8 4>; clocks = <&clkc 12>; clock-names = "ref_clk"; syscon = <&slcr>; };
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