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avnet-ultra96-rev1.dts
(379 B)
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zynqmp-clk-ccf.dtsi
(4.19 KB)
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zynqmp-zc1232-revA.dts
(1.1 KB)
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zynqmp-zc1254-revA.dts
(673 B)
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zynqmp-zc1275-revA.dts
(673 B)
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zynqmp-zc1751-xm015-dc1.dts
(2.02 KB)
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zynqmp-zc1751-xm016-dc2.dts
(2.33 KB)
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zynqmp-zc1751-xm017-dc3.dts
(2.29 KB)
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zynqmp-zc1751-xm018-dc4.dts
(2.25 KB)
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zynqmp-zc1751-xm019-dc5.dts
(1.49 KB)
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zynqmp-zcu100-revC.dts
(6.18 KB)
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zynqmp-zcu102-rev1.0.dts
(605 B)
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zynqmp-zcu102-revA.dts
(12.78 KB)
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zynqmp-zcu102-revB.dts
(775 B)
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zynqmp-zcu104-revA.dts
(3.48 KB)
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zynqmp-zcu106-revA.dts
(12.53 KB)
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zynqmp-zcu111-revA.dts
(10.38 KB)
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zynqmp.dtsi
(18.83 KB)
Editing: zynqmp-zcu102-revB.dts
// SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016 - 2018, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ #include "zynqmp-zcu102-revA.dts" / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; }; &gem3 { phy-handle = <&phyc>; phyc: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; /* Cleanup from RevA */ /delete-node/ ethernet-phy@21; }; /* Fix collision with u61 */ &i2c0 { i2c-mux@75 { i2c@2 { max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; /delete-node/ max15303@20; }; }; };
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